SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同...SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。展开更多
在高压交流输电系统(HVAC)发生短路故障时,极大可能会产生含暂态分量(short circuit current transient component,SCTC)的短路故障电流;当SCTC含量很大时甚至会产生短路电流的零点漂移现象,会对故障限流器(fault current limiter,FCL)...在高压交流输电系统(HVAC)发生短路故障时,极大可能会产生含暂态分量(short circuit current transient component,SCTC)的短路故障电流;当SCTC含量很大时甚至会产生短路电流的零点漂移现象,会对故障限流器(fault current limiter,FCL)的限流工作和参数设计造成很大的影响。针对上述问题,提出了一种SCTC泄能型故障限流器(SCTC energy drain type fault current limiter,SEDFCL)及其参数设计方法,可以加快SCTC的衰减。首先,分析了SEDFCL与SCTC的相互影响和SEDFCL的电磁路工作机理,并研究了SEDFCL场路耦合特性,对电磁参数进行了设计;然后,通过有限元仿真搭建了220 kV SEDFCL模型,探究了SEDFCL结构的有效性、合理性、RC参数的调节作用,以及故障情况下SEDFCL功能的有效性;最后,搭建一台小容量样机,建立试验平台并进行样机试验,证实SEDFCL结构和功能的有效性。与传统五柱式限流器(five-column hybrid excitation type FCL,FHETFCL)相比,SEDFCL将时间常数显著降低117.66%,限流效果提高6.29%。展开更多
This paper investigates the variation of electrical characteristic of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) under gate bias stress. The devices are subjected to positive and negative gate bias ...This paper investigates the variation of electrical characteristic of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) under gate bias stress. The devices are subjected to positive and negative gate bias stress for prolonged time periods. The effect of bias stress time and polarity on the transistor current equation is investigated and the underlying effects responsible for these variations are determined. Negative gate stress produces a positive shift in the threshold voltage. This can be noted as a variation from prior studies. Due to variation of power factor (n) from two, the integral method is implemented to extract threshold voltage (vt) and power factor (n). Effective, mobility (ueff), drain to source resistance (RDS) and constant k' is also extracted from the device characteristics. The unstressed value of n is deter-mined to be 2.5. The power factor increases with gate bias stress time. The distribution of states in the conduction band is revealed by the variation in power factor.展开更多
文摘在高压交流输电系统(HVAC)发生短路故障时,极大可能会产生含暂态分量(short circuit current transient component,SCTC)的短路故障电流;当SCTC含量很大时甚至会产生短路电流的零点漂移现象,会对故障限流器(fault current limiter,FCL)的限流工作和参数设计造成很大的影响。针对上述问题,提出了一种SCTC泄能型故障限流器(SCTC energy drain type fault current limiter,SEDFCL)及其参数设计方法,可以加快SCTC的衰减。首先,分析了SEDFCL与SCTC的相互影响和SEDFCL的电磁路工作机理,并研究了SEDFCL场路耦合特性,对电磁参数进行了设计;然后,通过有限元仿真搭建了220 kV SEDFCL模型,探究了SEDFCL结构的有效性、合理性、RC参数的调节作用,以及故障情况下SEDFCL功能的有效性;最后,搭建一台小容量样机,建立试验平台并进行样机试验,证实SEDFCL结构和功能的有效性。与传统五柱式限流器(five-column hybrid excitation type FCL,FHETFCL)相比,SEDFCL将时间常数显著降低117.66%,限流效果提高6.29%。
文摘This paper investigates the variation of electrical characteristic of indium gallium zinc oxide (IGZO) thin film transistors (TFTs) under gate bias stress. The devices are subjected to positive and negative gate bias stress for prolonged time periods. The effect of bias stress time and polarity on the transistor current equation is investigated and the underlying effects responsible for these variations are determined. Negative gate stress produces a positive shift in the threshold voltage. This can be noted as a variation from prior studies. Due to variation of power factor (n) from two, the integral method is implemented to extract threshold voltage (vt) and power factor (n). Effective, mobility (ueff), drain to source resistance (RDS) and constant k' is also extracted from the device characteristics. The unstressed value of n is deter-mined to be 2.5. The power factor increases with gate bias stress time. The distribution of states in the conduction band is revealed by the variation in power factor.
