Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering （DIBL） effect has been obtained by solving the two-dimensional （2D） Poisson＇s equation for the dual-channel 4H-SiC MESFET （DCFET）. Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytical model,we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET,which characterize the DIBL effect.The results show that they are significantly dependent on the drain bias,gate length as well as the thickness and doping concentration of the two channel layers.Based on this analytical model,the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.

UTBB SOI MOSFETs短沟道效应抑制技术

随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。

GaN异质结场效应管中栅、漏电压对电子气的控制

从自洽求解二维泊松方程和薛定谔方程出发,编制出计算GaN HFET内不同栅、漏电压下沟道能带、电子气密度及量子电容的软件,研究场效应管的电荷控制和DIBL。在异质结沟道阱研究中,改变栅电压算出的电子气密度及量子电容同C-V实验测试结果相吻合,证明求解薛定谔方程是研究异质结场效应管电荷控制的有效方法。考虑外沟道渗透到内沟道的电场梯度以后,算出了场效应管的电子气密度及量子电容。场效应管模拟算得的量子电容同实验测得的栅-源和栅-漏电容相吻合。研究了不同栅、漏电压和电场梯度渗透下的内沟道能带,发现漏电压引起的电场梯度渗透使内沟道能带下弯,导致阈值电压负移。证明阈值电压负移由外沟道渗透到内沟道的电场梯度产生,用自洽能带计算方法可算得漏电压引起的阈值电压负移。提出使用能带剪裁优化设计异质结构来抑制DIBL的新理念。同有限元变分软件的类MESFET模拟相比,新能带计算软件可以求得电荷控制中的量子行为。由此提出编制异质结场效应管模拟软件的设想。

GaN异质结场效应管中栅、漏电压对电子气的控制(续)

从自洽求解二维泊松方程和薛定谔方程出发,编制出计算GaN HFET内不同栅、漏电压下沟道能带、电子气密度及量子电容的软件,研究场效应管的电荷控制和DIBL。在异质结沟道阱研究中,改变栅电压算出的电子气密度及量子电容同C-V实验测试结果相吻合,证明求解薛定谔方程是研究异质结场效应管电荷控制的有效方法。考虑外沟道渗透到内沟道的电场梯度以后,算出了场效应管的电子气密度及量子电容。场效应管模拟算得的量子电容同实验测得的栅-源和栅-漏电容相吻合。研究了不同栅、漏电压和电场梯度渗透下的内沟道能带,发现漏电压引起的电场梯度渗透使内沟道能带下弯,导致阈值电压负移。证明阈值电压负移由外沟道渗透到内沟道的电场梯度产生,用自洽能带计算方法可算得漏电压引起的阈值电压负移。提出使用能带剪裁优化设计异质结构来抑制DIBL的新理念。同有限元变分软件的类MESFET模拟相比,新能带计算软件可以求得电荷控制中的量子行为。由此提出编制异质结场效应管模拟软件的设想。

非对称HALO-LDD掺杂石墨烯纳米条带场效应管的电学特性研究(英文)

随着器件沟道尺寸的不断缩小,短沟道效应(SCE)和漏致势垒降低效应(DIBL)对常规类MOSFET结构的石墨烯纳米条带场效应管(GNRFET)影响变大,从而引起器件性能下降。文中提出了一种新型采用非对称HALO-LDD掺杂结构的GNRFET,其能够有效抑制器件中SCE和DIBL,改善器件性能。并采用一种量子力学模型研究GNRFET的电学特性,该模型基于二维NEGF(非平衡格林函数)方程和Poisson方程自洽全量子数值解。结合器件的工作原理,研究了GNRFET的电学特性和器件结构尺寸效应,通过与采用其他掺杂结构的GNRFET的电学特性对比分析,发现这种掺杂结构的石墨烯纳米条带场效应管具有更低的泄漏电流。

22nm技术节点异质栅MOSFET的特性研究

研究了22 nm栅长的异质栅MOSFET的特性,利用工艺与器件仿真软件Silvaco,模拟了异质栅MOSFET的阈值电压、亚阈值特性、沟道表面电场及表面势等特性,并与传统的同质栅MOSFET进行比较。分析结果表明,由于异质栅MOSFET的栅极由两种不同功函数的材料组成,因而在两种材料界面附近的表面沟道中增加了一个电场峰值,相应地漏端电场比同质栅MOSFET有所降低,所以在提高沟道载流子输运效率的同时也降低了小尺寸器件的热载流子效应。此外,由于该器件靠近源极的区域对于漏压的变化具有屏蔽作用,从而有效抑制了小尺寸器件的沟道长度调制效应,但是由于其亚阈值特性与同质栅MOSFET相比较差,导致漏致势垒降低效应(DIBL)没有明显改善。

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II

This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I

Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications.

Enhanced radiation-induced narrow channel effects in 0.13-μm PDSOI nMOSFETs with shallow trench isolation

Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor（nMOSFET） is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect（RINCE）.The analysis based on a charge sharing model and three-dimensional technology computer aided design（TCAD） simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.

Simulation of electrical characteristics and structural optimization for small-scaled dual-gate GeOI MOSFET with high-k gate dielectric

The influences of the main structure and physical parameters of the dual-gate GeOl MOSFET on the device performance are investigated by using a TCAD 2D device simulator. A reasonable value range of germanium （Ge） channel thickness, doping concentration, gate oxide thickness and permittivity is determined by analyzing the on-state current, off-state current, short channel effect （SCE） and drain-induced barrier lowering （DIBL） effect of the GeOI MOSFET. When the channel thickness and its doping concentration are 10-18 nm and （5-9）×1017 cm-3, and the equivalent oxide thickness and permittivity of the gate dielectric are 0.8-1 nm and 15-30, respectively, excellent device performances of the small-scaled GeOI MOSFET can be achieved： on-state current of larger than 1475 μA/μm, off-state current of smaller than 0.1μA/μm, SCE-induced threshold-voltage drift of lower than 60 mV and DIBL-induced threshold-voltage drift of lower than 140 mV.

Performance analysis of charge plasma based dual electrode tunnel FET

This paper proposes the charge plasma based dual electrode doping-less tunnel FET （DEDLTFET）. The paper compares the device performance of the conventional doping-less TFET （DLTFET） and doped TFET （DGTFET）. DEDLTEFT gives the superior results with high ON state current （/ON - 0.56 mA/um）, ION/IoFv ratio - 9.12 ×1013 and an average subthreshold swing （AV-SS -- 48 mV/dec）. The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.