Anomalous Channel Length Dependence of Hot-Carrier-Induced Saturation Drain Current Degradation in n-Type MOSFETs

The dependencies of hot-carrier-induced degradations on the effective channel length Lch,eff are investigated for n-type metal-oxide-semiconductor field effect transistor （MOSFETs）. Our experiments find that, with decreasing Lch,eff, the saturation drain current （Iasat ） degradation is unexpectedly alleviated. The further study demonstrates that the anomalous Lch,eff dependence of Idsat degradation is induced by the increasing influence of the substrate current degradation on the lazar degradation with Lch,eff reducing.

Enhanced radiation-induced narrow channel effects in 0.13-μm PDSOI nMOSFETs with shallow trench isolation

Total ionizing dose responses of different transistor geometries after being irradiated by ^（60）Co γ-rays, in 0.13-μm partially-depleted silicon-on-insulator（PD SOI） technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor（nMOSFET） is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect（RINCE）.The analysis based on a charge sharing model and three-dimensional technology computer aided design（TCAD） simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.

Experiment and simulation on degradation and burnout mechanisms of SiC MOSFET under heavy ion irradiation

Experiments and simulation studies on 283 MeV I ion induced single event effects of silicon carbide(SiC) metal–oxide–semiconductor field-effect transistors(MOSFETs) were carried out. When the cumulative irradiation fluence of the SiC MOSFET reached 5×10^(6)ion·cm^(-2), the drain–gate channel current increased under 200 V drain voltage, the drain–gate channel current and the drain–source channel current increased under 350 V drain voltage. The device occurred single event burnout under 800 V drain voltage, resulting in a complete loss of breakdown voltage. Combined with emission microscope, scanning electron microscope and focused ion beam analysis, the device with increased drain–gate channel current and drain–source channel current was found to have drain–gate channel current leakage point and local source metal melt, and the device with single event burnout was found to have local melting of its gate, source, epitaxial layer and substrate. Combining with Monte Carlo simulation and TCAD electrothermal simulation, it was found that the initial area of single event burnout might occur at the source–gate corner or the substrate–epitaxial interface, electric field and current density both affected the lattice temperature peak. The excessive lattice temperature during the irradiation process appeared at the local source contact, which led to the drain–source channel damage. And the excessive electric field appeared in the gate oxide layer, resulting in drain–gate channel damage.

Engineering Strategies on Flood Control in Middle Reach of Yangtze River, China

Flood disaster has been a serious hidden danger since the ancient time. The essential cause for the fact that floods have not been eliminated for hundreds of years is that time honored strategies do not suit the cases of flood prevention. In the view of geological environmental analyses of flood formation and from the synthesis of experiences gained in flood control in the past hundreds of years, sluggish draining of flood, silt sedimentation in channel and building levee blindly constitute the main cause of intractable flood for a long time in the middle reach of the Yangtze River. Draining away silt and water is the only way to stamping out flood disaster. Opening up artificial waterways for flood diversion, draining away the silt of channel into the polders, and storing the flood water are important engineering measures for the flood control and damage reduction.

Insights into channel potentials and electron quasi-Fermi potentials for DG tunnel FETs

A detailed investigation carried out, with the help of extensive simulations using the TCAD device simulator Sentaurus, with the aim of achieving an understanding of the effects of variations in gate and drain potentials on the device characteristics of a silicon double-gate tunnel field effect transistor（Si-DG TFET） is reported in this paper. The investigation is mainly aimed at studying electrical properties such as the electric potential, the electron density, and the electron quasi-Fermi potential in a channel. From the simulation results, it is found that the electrical properties in the channel region of the DG TFET are different from those for a DG MOSFET. It is observed that the central channel potential of the DG TFET is not pinned to a fixed potential even after the threshold is passed（as in the case of the DG MOSFET）; instead, it initially increases and later on decreases with increasing gate voltage, and this is also the behavior exhibited by the surface potential of the device. However, the drain current always increases with the applied gate voltage. It is also observed that the electron quasi-Fermi potential（e QFP）decreases as the channel potential starts to decrease, and there are hiphops in the channel e QFP for higher applied drain voltages. The channel regime resistance is also observed for higher gate length, which has a great effect on the I–V characteristics of the DG TFET device. These channel regime electrical properties will be very useful for determining the tunneling current; thus these results may have further uses in developing analytical current models.