A Novel Integrated Circuit Driver for LED Lighting

A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driver. In this way, a novel average current mode can be set up to take the place ordinary peak current control mode. In addition, a BUCK low-level topology was adopted, too. It can be used to drive up to eight 1 W HB LED lights with 350 mA constant current. In this way, the LED driver displays high performance, in which output current with less 1% error and total efficiency as high as 96%. The feasibility of the design has been verified by actual measurement on the fabricated chip.

Influences of Switching Jitter on the Operational Performances of Linear Transformer Drivers-Based Drivers

A whole circuit model of a linear transformer drivers （LTD） module composed of 60 cavities in series was developed in the software PSPICE to study the influence of switching jitter on the operational performances of LTDs. In the model, each brick in each cavity is capable of operating with jitter in its switch. Additionally, the manner of triggering cables entering into cavities was considered. The performances of the LTD module operating with three typical cavity-triggering sequences were simulated and the simulation results indicate that switching jitter affects slightly the peak and starting time of the output current pulse. However, the enhancement in switching jitter would significantly lengthen the rise time of the output current pulse. Without considering other factors, a jitter lower than 10 ns may be necessary for the switches in the LTD module to provide output current parameters with an acceptable deviation.

Numerical Analysis of the Output-Pulse Shaping Capability of Linear Transformer Drivers

Output-pulse shaping capability of a linear transformer driver （LTD） module under different conditions is studied, by conducting the whole circuit model simulation by using the PSPICE code. Results indicate that a higher impedance profile of the internal transmission line would lead to a wider adjustment range for the output current rise time and a narrower adjustment range for the current peak. The number of cavities in series has a positive effect on the output- pulse shaping capability of LTD. Such an improvement in the output-pulse shaping capability can primarily be ascribed to the increment in the axial electric length of LTD. For a triggering time interval longer than the time taken by a pulse to propagate through the length of one cavity, the output parameters of LTD could be improved significantly. The present insulating capability of gas switches and other elements in the LTD cavities may only tolerate a slightly longer deviation in the triggering time interval. It is feasible for the LTD module to reduce the output current rise time, though it is not useful to improve the peak power effectively.

Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.

Design and Verification of a High Performance LED Driver with an Efficient Current Sensing Architecture

A high power buck-boost switch-mode LED driver delivering a constant 350 mA with a power efficient current sensing scheme is presented in this paper. The LED current is extracted by differentiating the output capacitor voltage and maintained by a feedback. The circuit has been fabricated in a standard 0.35 μm AMS CMOS process. Measurement results demonstrated a power-conversion efficiency over 90% with a line regulation of 8%/V for input voltage of 3.3 V and current output between 200 mA and 350 mA.

A Review of PVT Compensation Circuits for Advanced CMOS Technologies

The recent high-performance interfaces like DDR2, DDR3, USB and Serial ATA require their output drivers to provide a minimum variation of rise and fall times over Process, Voltage, and Temperature (PVT) and output load variations. As the interface speed grows up, the output drivers have been important component for high quality signal integrity, because the output voltage levels and slew rate are mainly determined by the output drivers. The output driver impedance compliance with the transmission line is a key factor in noise minimization due to the signal reflections. In this paper, the different implementations of PVT compensation circuits are analyzed for cmos45nm and cmos65nm technology processes. One of the considered PVT compensation circuits uses the analog compensation approach. This circuit was designed in cmos45nm technology. Other two PVT compensation circuits use the digital compensation method. These circuits were designed in cmos65nm technology. Their electrical characteristics are matched with the requirements for I/O drivers with respect to DDR2 and DDR3 standards. DDR2 I/O design was done by the Freescale wireless design team for mobile phones and later was re-used for other high speed interface designs. In conclusion, the advantages and disadvantages of considered PVT control circuits are analyzed.

A Hybrid GA-SQP Algorithm for Analog Circuits Sizing

This study presents a hybrid algorithm obtained by combining a genetic algorithm (GA) with successive quadratic sequential programming (SQP), namely GA-SQP. GA is the main optimizer, whereas SQP is used to refine the results of GA, further improving the solution quality. The problem formulation is done in the framework named RUNE (fRamework for aUtomated aNalog dEsign), which targets solving nonlinear mono-objective and multi-objective optimization problems for analog circuits design. Two circuits are presented: a transimpedance amplifier (TIA) and an optical driver (Driver), which are both part of an Optical Network-on-Chip (ONoC). Furthermore, convergence characteristics and robustness of the proposed method have been explored through comparison with results obtained with SQP algorithm. The outcome is very encouraging and suggests that the hybrid proposed method is very efficient in solving analog design problems.

一种用于光隔离IGBT栅极驱动的智能型LED驱动电路

采用双极型工艺设计了一种智能型高速LED驱动电路,可用于光隔离IGBT栅极驱动芯片的输入驱动。该设计采用一种新型逻辑门结构来实现信号传输、故障反馈以及外部置位等功能,同时达到降低信号传输延迟时间的目的。测试结果表明,在常温条件下,LED驱动电路的输入信号传输延迟时间为70 ns,复位信号有效到故障消除的延迟时间为4.59μs。所设计的驱动电路能够满足光耦隔离IGBT栅极驱动芯片的使用要求。

亚纳秒级上升沿窄脉冲驱动电路与模拟仿真

针对半导体激光二极管(LD)驱动电路中存在的上升沿缓慢问题,设计了一种具有亚纳秒上升沿的窄脉冲电路。从理论方面分析了回路中电感、电容等参数对输出激光脉冲上升沿的影响,驱动电路以内置驱动的GaN集成模块作为主开关进行电路的合理设计驱动半导体激光二极管;利用现场可编程门阵列作为控制核心设计时序信号,实现LD脉宽和重频的精确调节;以ADN8831驱动热电制冷器(TEC)实现LD精确恒温控制。通过模拟仿真和实验验证,获得了亚纳秒级的脉冲前沿,脉冲宽度5 ns至15 ns可调,重复频率1 kHz至10 kHz可调,LD的温度设定为25℃至26℃,12 h功率稳定性RMS测试值为0.51%。

基于WMS的可调谐半导体激光器驱动与温控电路设计

针对可调谐半导体激光器工作时,其工作电流和工作温度的波动导致激光器的输出的波长和功率不能保持恒定的问题,设计了一套基于STM32F407为主控芯片联合FPGA的半导体激光器小型化驱动与温控电路。通过与上位机交互,系统可实现激光器驱动电流和工作温度的连续可调,使半导体激光器的输出光的波长在最佳的范围内。经过测试,系统的驱动模块电流稳定度为0.075%,电流的实际值与理论值之间的相对误差平均值为0.538%;温度电路的稳定度在0.03℃,完全满足实际应用需求。

一种灵活可靠的IGBT驱动电路设计

在当今减碳排放背景下,全控型功率器件IGBT以优异的性能广泛用于各种变流器中,有效可靠的驱动电路对IGBT的安全工作至关重要,特别是大功率应用场合。针对大功率IGBT应用中对驱动电路灵活可靠的要求,设计了一种基于智能集成光耦驱动器ACPL-332J的IGBT驱动保护电路,分析了ACPL-332J的各项参数,并以ACPL-332J为核心设计了驱动电路。以英飞凌FF600R12ME4为应用IGBT,通过双脉冲试验、短路试验验证了设计电路驱动及保护的有效性。

集成结温在线监测功能的IGBT智能驱动器

结温是表征功率器件寿命的重要参数,对功率器件结温进行监测具有重要意义。基于热敏电参数法,选取对温度敏感的电参量饱和导通压降V_(CE(sat))作为研究对象,在IGBT驱动器中集成高精度结温参数测量电路,使系统可在线监测功率器件结温。同时为了得到更加精准的热-电参量对应关系,通过分段拟合的方式对IGBT模块在工作状态下结温与V_(CE(sat))的关系进行数学建模。在此基础上,还设计了相应的退饱和检测电路和分级驱动电路。经过实验验证,最终解决了传统结温测量方式工程应用性差的问题,提高了参数采集精度,将热敏电参数的结温预测误差控制在±5℃以内。

一种高频单片GaN DC-DC降压转换器设计

基于全耗尽型(D-mode)0.25μm硅基氮化镓(GaN-on-Si)工艺,设计了一款高频单片GaN DC-DC降压转换器芯片。该芯片集成了驱动电路和半桥功率级电路,驱动电路中电平放大功能通过有源上拉结构实现,在100~200 MHz频率范围内,单片GaN DC-DC降压转换器可直接被0.7 V的高速脉冲信号控制,无需片外模块,其峰值功率级效率达到92.2%,峰值总效率达到84.24%,峰值功率为7.7 W。相较于前期工作,芯片工作范围从100 MHz提升至200 MHz,在保证芯片效率性能的情况下,实现了对工作频率的大幅提升。

一种40Mbps传输速率的光纤数据接口芯片设计

阐述设计的一种40Mbps光纤数据接口的芯片,传输速率是20Mbps光纤数据接口芯片的1.6倍,传输延时达到20ns,抖动时间稳定在0.04ns,占空比达到44.19%,信号传输能力稳定且输出信号不失真。在此基础上,将芯片和LED封装在一起,该芯片可以为LED稳定提供3.5~4mA的工作电流,降低整体功耗。该芯片适合数字光学数据链接和数字音频接口。

快脉冲直线变压器初级放电单元开关电容一体化设计

开关电容器组成的初级放电支路是快脉冲直线变压器(FLTD)的基本单元,在输出电流幅值和前沿不变的前提下,降低单元回路电感可有效减少放电支路及气体开关的使用数量,从而提高FLTD的整体可靠性。因此,设法降低初级支路电感是FLTD关键技术。基于开关电容一体化技术研制了一台低电感FLTD初级放电单元,采用环形高压脉冲电容器作为能量储能元件,其工作电压100 kV,电容量39.6 nF,内电感8.8 nH。实验测试了初级放电单元的工作特性,结果表明:在±50 kV工作电压下,初级放电单元的短路电流幅值40 kA,前沿50 ns,回路电感为101 nH;在±80 kV工作电压下,初级放电单元对匹配负载的输出电流幅值为30 kA,前沿66 ns。

GaN驱动芯片的增强型抗干扰欠压保护电路

针对汽车电子高性能GaN驱动芯片需求,为解决GaN器件栅极存在低压误开、高共模瞬态、抗干扰能力差等问题,提出了一种低温度系数、低功耗、高回差电压、具有双重比较的欠压保护电路。该电路采用双重比较参考电路,设置合理的比较电压,增大电路回差电压,极大提高了电路的抗干扰能力。电源上电至预设电压后,系统解除保护锁定,GaN器件通路开启,电源驱动后级GaN器件栅极,实现GaN器件欠压保护功能,提高稳定性。采用0.18μm BCD工艺进行设计。仿真结果表明,电源上电至8.5 V时,电路解除欠压保护功能,带隙基准电路输出1.5×10^(-5)/℃高精度5 V电压至GaN驱动电路栅端。电源下电至8 V时,电路启动欠压保护功能,芯片系统关断,实现GaN器件保护功能。回差电压为0.5 V,静态电流为60μA。该欠压保护电路满足低温度系数、低功耗、高回差电压等要求。

一种无桥高增益单级LED驱动电路及其混合控制策略

中小功率的LED驱动电源中,传统两级LED驱动电源存在体积大、成本高以及传统Boost PFC电路在低压输入时导通损耗大等问题。为此提出一种由无桥二次型Boost PFC电路和DC-DC LLC电路集成的无桥高增益单级LED驱动电路,实现了高电压增益、功率开关器件软开关、一套控制电路和高电路转换效率。针对单级电路在电网输入电压变化引起直流母线电压变动范围大等问题,设计一种适用于所提电路的APWM-PFM混合控制策略,并对混合控制原理和控制过程进行详细分析。最后设计一台200 W的实验样机,在输入电压80~120 Vrms范围内,占空比最大为0.5,最大电压增益为6.7,直流母线电压基于网侧特性和LLC电路特性设计在700 V以内,样机的功率因数值均高于0.990,THD均低于15%。在满载条件下,110 Vrms输入时,样机效率为93.20%,相比于传统无桥PFC,电压增益提高了2.21倍,实现了高电压增益和软开关,有效提升了在低压输入条件下的电路转换效率。仿真和实验结果验证了所提出电路和控制方法的有效性。

基于ARM处理器的细分步进电机驱动器设计

基于ARM处理器MM32SPIN0280设计一款细分步进电机驱动器。主要特点包括外置MOS管驱动器、半桥驱动电路和电流采集电路,实现电流环控制电机。详细分析步进电机衰减模式、电流采样时刻和恒定力矩矢量控制方法。对自举电路和驱动电阻进行功能阐述和定量计算,为实际电路设计提供理论依据。针对软件讨论PWM输出和采样时刻设计,以及恒定力矩矢量控制的实现方法。通过实际电机线圈电流测量,展示了高细分驱动对恒定力矩和小电流波动的优势。通过对比16和2细分情况下的电流波形,证明高细分运行时电机扭矩更稳定,噪音更小。本设计为小型化、高性能步进电机驱动器的开发提供了有价值的参考。

一种BCM Boost PFC电路的VCFF控制策略

临界导通模式Boost功率因素校正(PFC)电路通常采用恒定导通时间(COT)控制策略,导致开关频率的变化与输入电压、输出功率以及电感有关,轻载下过高的开关频率将影响电路的转换效率,故提出一种谷底计数频率反走(VCFF)控制策略。通过检测MOS管两端电压谷底计数,使电路轻载时工作在断续模式,从而降低开关频率以提升轻载效率。实验结果表明,相比于COT控制策略,所提控制策略能够有效提高轻载效率。输入电压为220 Vrms下,10%~50%负载时效率在0.96以上。

基于无感FOC的一体式无刷电机控制驱动器的电路系统

针对无感方波控制时,存在控制精度低,电流采样误差大,低速启动性能较差等问题。设计了一种基于无感FOC的一体式无刷电机控制驱动器的电路系统。系统以TI公司的大电流栅极驱动器DRV8301为预驱核心,设计了数模耦合电路及高端电流采样电路,实现了控制器和驱动器的高度集成,减少了电流采样误差。经实验测试表明,所设计的电路系统能够实现FOC正弦波的稳定输出,持续输出功率可达上千瓦,实时电流监测误差不超过1%,具有体积小、高爆发、高精度控制、响应速度快等优点,可广泛用于工业自动化控制等领域。