Ambipolar performance improvement of the C-shaped pocket TFET with dual metal gate and gate–drain underlap

Dual-metal gate and gate–drain underlap designs are introduced to reduce the ambipolar current of the device based on the C-shaped pocket TFET(CSP-TFET).The effects of gate work function and gate–drain underlap length on the DC characteristics and analog/RF performance of CSP-TFET devices,such as the on-state current(I_(on)),ambipolar current(I_(amb)),transconductance(g_(m)),cut-off frequency(f_(T))and gain–bandwidth product(GBP),are analyzed and compared in this work.Also,a combination of both the dual-metal gate and gate–drain underlap designs has been proposed for the C-shaped pocket dual metal underlap TFET(CSP-DMUN-TFET),which contains a C-shaped pocket area that significantly increases the on-state current of the device;this combination design substantially reduces the ambipolar current.The results show that the CSP-DMUN-TFET demonstrates an excellent performance,including high I_(on)(9.03×10^(-4)A/μm),high I_(on)/I_(off)(~10^(11)),low SS_(avg)(~13 mV/dec),and low I_(amb)(2.15×10^(-17)A/μm).The CSP-DMUN-TFET has the capability to fully suppress ambipolar currents while maintaining high on-state currents,making it a potential replacement in the next generation of semiconductor devices.

Key technologies for dual high-k and dual metal gate integration

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiOx. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1（NH4OH：H2O2：H2O = 1 ： 1 ： 5） and DHF-based solution for the selective removing of n MOS TaN and Hf Si ON and by BCl3-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON.After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl3/SF6/O2/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl3/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal-semiconductor field-effect transistor

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET （DMGFET） are investigated and the analytical models to describe the drain-induced barrier lowering （DIBL） effect are derived by solving one- and two- dimensional Poisson＇s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering （DIBL） effect. The calculated results reveal that the dual material gate （DMG） structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor （SMGFET）.

部分耗尽异质环栅场效应晶体管阈值电压模型

为抑制短沟道效应和解决载流子传输效率低的问题,提出了部分耗尽异质环栅金属氧化物半导体场效应晶体管(MOSFET)结构(DMSG),并建立了器件的表面电势和阈值电压解析模型。异质环栅由两种具有不同功函数的材料无缝拼接形成,能在沟道中产生电场峰值,降低漏端电场,并屏蔽漏压对最小表面势的影响。通过为沟道耗尽层各区建立柱坐标下电势泊松方程和相应的边界条件方程,采用径向抛物线近似对偏微分方程进行降维和解析求解技术,获得了DMSG结构的解析模型。仿真结果表明,与传统的部分耗尽环栅器件相比,DMSG结构载流子传输效率高,短沟道效应、漏致势垒降低效应和热载流子效应抑制能力强;所建解析模型与数值仿真软件的相对误差小于5%。

基于SiC和Si器件的燃料电池汽车DC-DC变换器的性能

为实现燃料电池汽车输出电压、功率的调节与控制,采用了一种交错式双Boost电路的大功率直流-直流(DC-DC)变换器,其中应用了Si和SiC功率器件。基于电路损耗计算和效率仿真手段,对比分析了全SiC[金属-氧化物半导体场效应晶体管(MOSFET)器件、SiC二极管]、SiC MOSFET和Si二极管的混合器件和全硅Si[绝缘栅双极型晶体管(IGBT)器件、Si二极管]的变换器在电路损耗。结果表明:Si IGBT的开通和关断损耗约是SiC MOSFET的3倍和10倍,在不同工况下,全SiC变换器的转换效率比全Si变换器高1%~3.1%。因而,SiC功率器件在大功率DC-DC变换器的应用中,能够提高功率密度、可靠性和动力系统工作效率。

蚀刻设备的现状与发展趋势

概述了蚀刻技术与设备的现状,针对32nm技术节点器件制程对蚀刻设备在双重图形蚀刻、高k/金属栅材料、金属硬掩膜及进入后摩尔时代三维封装的通孔硅技术(TSV)方面挑战,介绍了蚀刻设备的发展趋势。

SOI CMOS器件研究

利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。

A novel design approach of charge plasma tunnel FET for radio frequency applications

In this paper, the impact of extra electron source(EES) and dual metal gate engineering on conventional charge plasma TFET(CP-TFET) have been done for improving DC and analog/RF parameters. CP-TFET structure is upgraded to double source CP-TFET(DS-CP-TFET) by placing an EES below the source/channel junction for enhancing the device performance in terms of driving current and RF figures of merit(FOMs). But, in spite of these pros, the approach is having cons of higher leakage current similar to MOSFET and negative conductance(inherent nature of TFET). Both the issues have been resolved in the double source dual gate CP-TFET(DS-DG-CP-TFET) by gate workfunction engineering and drain underlapping respectively. Additionally,for getting the optimum performance of DS-DG-CP-TFET, the device sensitivity has been investigated in terms of position of EES,length of drain electrode and workfunction of gate electrode 1(GE1).

Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon–germanium substrates

The present work gives some insight into the subthreshold behaviour of short-channel double-material- gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formu- lation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLASTM by Silvaco Inc.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity:a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension （ISE） cylindrical gate all around （CGAA） Schottky barrier （SB） MOSFET has been reported, to eliminate the suicidal ambipolar behavior （bias-dependent OFF state leakage current） of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The IoN/Iovr： of ISE-CGAA-SB-MOS- FET increases by 1177 times and offers steeper subthreshold slope （-60 mV/decade）. However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

基于异质双栅电极结构提高碳纳米管场效应晶体管电子输运效率

为改善碳纳米管场效应晶体管(CNTFET)器件性能,提高电子输运效率,提出了一种异质双金属栅(HDMG)电极结构CNTFET器件.通过对单金属栅(SMG)-CNTFET器件输运模型的适当修改,实现了对HDMG-CNTFET器件电子输运特性的研究.研究结果表明,对于所提出的HDMG结构器件,如果固定源端金属栅S-gate的功函数WGS使其等于本征CNT的功函数,而选取漏端金属栅D-gate的功函数WGd,使其在一定范围内小于WGS,可优化器件沟道中的电场分布,提高器件沟道电子平均输运速率;同时由于HDMG-CNTFET的D-gate对沟道电势具有调制作用,使该器件阈值电压降低,导致在相同的工作电压下,HDMG-CNTFET器件具有更大的通态电流;而D-gate对漏电压的屏蔽作用又使HDMG-CNTFET与SMG-CNTFET相比具有更好的栅控能力及减小漏极感应势垒降低效应、热电子效应和双极导电性等优点.本研究通过合理选取HDMG-CNTFET双栅电极的功函数,有效克服了现有研究中存在的改善CNTFET性能需要以减小通态电流为代价的不足,重要的是提高了器件的电子输运效率,进而可提高特征频率、减小延迟时间,有利于将CNTFET器件应用于高速/高频电路.