Since the satellite communication goes in the trend of high-frequency and fast speed, the coefficients updating and the precision of the traditional pre-distortion feedback methods need to be further improved. On this...Since the satellite communication goes in the trend of high-frequency and fast speed, the coefficients updating and the precision of the traditional pre-distortion feedback methods need to be further improved. On this basis, this paper proposes dual loop feedback pre-distortion, which uses two first-order Volterra filter models to reduce the computing complexity and a dynamic error adjustment model to construct a revised feedback to ensure a better pre-distortion performance. The computation complexity, iterative convergence speed and precision of the proposed method are theoretically analyzed. Simulation results show that this dual loop feedback pre-distortion can speed the updating of coefficients and ensure the linearity of the amplifier output.展开更多
This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and con...This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and control timing strategy is used to improve the system dynamic response. Simulation and experimental results presented in the paper verified the validity of the proposed control scheme.展开更多
The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock ...The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.展开更多
A wideband variable gain amplifier （VGA） implemented in 0.13 μm CMOS technology is presented. To optimize noise performance, an active feedback amplifier with 15 dB fixed gain is put in the front, followed by modif...A wideband variable gain amplifier （VGA） implemented in 0.13 μm CMOS technology is presented. To optimize noise performance, an active feedback amplifier with 15 dB fixed gain is put in the front, followed by modified Cherry-Hooper amplifiers in cascade providing variable gain, which adopt dual loop feedback for band- width extension. Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation, respectively. Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of-29 dBm at the lowest gain state, while the minimum noise figure is 9 dB at the highest gain state. The core VGA （without test buffer） consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.展开更多
文摘Since the satellite communication goes in the trend of high-frequency and fast speed, the coefficients updating and the precision of the traditional pre-distortion feedback methods need to be further improved. On this basis, this paper proposes dual loop feedback pre-distortion, which uses two first-order Volterra filter models to reduce the computing complexity and a dynamic error adjustment model to construct a revised feedback to ensure a better pre-distortion performance. The computation complexity, iterative convergence speed and precision of the proposed method are theoretically analyzed. Simulation results show that this dual loop feedback pre-distortion can speed the updating of coefficients and ensure the linearity of the amplifier output.
文摘This paper presents a novel digital dual-loop control scheme of the PWM(PUlse width modulate)inverter. Deadbeat control technique are employed to enhance the performance. Half switching period delayed sampling and control timing strategy is used to improve the system dynamic response. Simulation and experimental results presented in the paper verified the validity of the proposed control scheme.
文摘The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.
基金Project supported by the National High Technology Research and Development of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University
文摘A wideband variable gain amplifier （VGA） implemented in 0.13 μm CMOS technology is presented. To optimize noise performance, an active feedback amplifier with 15 dB fixed gain is put in the front, followed by modified Cherry-Hooper amplifiers in cascade providing variable gain, which adopt dual loop feedback for band- width extension. Negative capacitive neutralization and capacitive source degeneration are employed for Miller effect compensation and DC offset cancellation, respectively. Measurement results show that the proposed VGA achieves a 35 dB gain tuning range with an upper 3-dB bandwidth larger than 3 GHz and the input 1 dB compression point of-29 dBm at the lowest gain state, while the minimum noise figure is 9 dB at the highest gain state. The core VGA （without test buffer） consumes 32 mW from 1.2 V power supply and occupies 0.48 mm2 area.
