Dual Material Gate SOI MOSFET with a Single Halo

In order to suppress drain-induced barrier lowering in dual material gate SOI MOSFETs,halo doping is used in the channel near the source. Two-dimensional analytical models of surface potential and threshold voltage for the novel SOI MOSFET are developed based on the explicit solution of the two-dimensional Poisson＇s equation. Its characteristic improvement is investigated. It is concluded that the novel structure exhibits better suppression of drain-induced barrier lowering and higher carrier transport efficiency than conventional dual material gate SOI MOSFETs. Its drain-induced barrier lowering decreases with increasing halo doping concentration but does not change monotonically with halo length. The analytical models agree well with the two-dimensional device simulator MEDICI.

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

Subthreshold current model of fully depleted dual material gate SOI MOSFET

Dual material gate SOI MOSFET with asymmetrical halo can suppress short channel effect and increase carriers transport efficiency. The analytical model of its subthreshold drain current is derived based on the explicit solution of two-dimensional Poisson’s equation in the depletion region. The model takes into consideration the channel length modulation effect and the contribution of the back channel current component. Its validation is verified by comparision with two dimensional device simulator MEDICI.

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal-semiconductor field-effect transistor

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET （DMGFET） are investigated and the analytical models to describe the drain-induced barrier lowering （DIBL） effect are derived by solving one- and two- dimensional Poisson＇s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering （DIBL） effect. The calculated results reveal that the dual material gate （DMG） structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor （SMGFET）.

Analytical Modeling of Dual Material Gate SOI MOSFET with Asymmetric Halo

A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with different work functions by making them contacting laterally, and the channel is more heavily doped near the source than in the rest. Using a three-region polynomial potential distribution and a universal boundary condition, a two-dimensional analytical model for the fully depleted silicon-on-insulator MOSFET is developed based on the explicit solution of two-dimensional Poisson＇s equation. The model includes the calculation of potential distribution along the channel and subthreshold current. The performance improvement of the novel silicon-on-insulator MOSFET is examined and compared with the traditional silicon-on-insulator MOSFET using the analytical model and two-dimensional device simulator MEDICI. It is found that the novel silicon-on-insulator MOSFET could not only suppress short channel effect, but also increase cartier transoort efficiency noticeably. The derived analytical model agrees well with MEDICI.

Performance investigations of novel dual-material gate(DMG) MOSFET with dielectric pockets(DP)

Dual-material gate MOSFET with dielectric pockets (DMGDP MOSFET) is proposed to eliminate the potential weakness of the DP MOSFET for CMOS scaling toward the 32 nm gate length and beyond. The short-channel effects (SCE) can be effectively suppressed by the insulator near the source/drain regions. And the suppression capability can be even better than the DP MOSFET due to the drain bias absorbed by the screen gate. The speed performance and electronic characteristics of the DMGDP MOSFET are comprehensively studied. Compared to the experimental data from Jurczak et al., the DMGDP PMOSFET exhibits good subthreshold characteristics and the on-state current is almost the twice that of the DP PMOSFET. The intrinsic delay of the NMOS reaches 21% greater than the DP MOSFET for 32 nm node. The higher fT of 390 GHz is achieved, which is a 32% enhancement in comparison with the DP MOSFET when the gate length is 50 nm. Finally, the design guideline and the optimal regions of the DMGDP MOSFET are discussed.

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET （IMOS） is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope （SS） of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET （DG-IMOS） is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG （dual material gate） DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better IoN, ION/IoFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized perform- ance is achieved including ION/IoFF ratio of 2.87 × 10^9 A/μm with/ON as 11.87 × 10^-4 A/μm and transconductance of 1.06× 10^-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.

A two-dimensional analytical model of fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs

On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are： transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits （FOMs） are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate （L 1） for a given gate length （L） are also studied and the optimum lengths La under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.

3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET

The evolution of the traditional metal oxide semiconductor field effect transistor(MOSFET) from planar single gate devices into 3 D multiple gates has led to higher package density and high current drive.However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects(SCEs).In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented.The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson’s equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model.The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET（HD_DMG_DLTFET）. It is compared with conventional doping-less TFET（DLTFET） and dual material gate doping-less TFET（DMG_DLTFET） on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current（I_（ON） =94 μA/ μm）, I_（ON）/I_（OFF）（≈1.36×10^（13））, point（≈3 mV/dec） and average subthreshold slope（AV-SSD40.40 mV/dec）. The proposed device offers low total gate capacitance（C_（gg）/ along with higher drive current. However, with a better transconductance（g_m） and cut-off frequency（f_T）, the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage（V_（EA）/ and output conductance（gd/ are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices.From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

基于二维电势分布的一种新型复合多晶硅栅LDMOS阈值电压模型

本文提出了一种新型的复合多晶硅栅LDMOS结构.该结构引入栅工程的概念,将LDMOST的栅分为n型多晶硅栅和p型多晶硅栅两部分,从而提高器件电流驱动能力,抑制SCEs(short channel effects)和DIBL(drain-inducedbarrier lowering).通过求解二维泊松方程建立了复合多晶硅栅LDMOST的二维阈值电压解析模型.模型考虑了LDMOS沟道杂质浓度分布和复合栅功函数差的共同影响,具有较高的精度.与MEDICI数值模拟结果比较后,模型得以验证.

异质栅非对称Halo SOI MOSFET亚阈值电流模型

在沟道源端一侧引入高掺杂Halo结构的异质栅SOI MOSFET,可以有效降低亚阈值电流.通过求解二维泊松方程,为该器件建立了亚阈值条件下的表面势模型.利用常规漂移-扩散理论,在表面势模型的基础上,推导出新结构器件的亚阈值电流模型.为了求解简单,文中给出了一种分段近似方法,从而得到表面势的解析表达式.结果表明,所得到的表面势解析表达式和确切解的结果高度吻合.二维器件数值模拟器ISE验证了通过表面势解析表达式得到的亚阈值电流模型,在亚阈值区二者所得结果吻合得很好.

复合多晶硅栅LDMOS的设计

提出了一种应用于射频领域的复合多晶硅栅LDMOS结构,并提出了具体的工艺实现方法。此结构采用栅工程的概念,设计的栅由S-gate和D-gate两块并列组成,S-gate用高功函数P型多晶硅材料,D-gate用低功函数N型多晶硅材料。MEDICI模拟结果表明,该结构能够降低沟道末端和漏极附近的最高电场强度,提高器件的跨导和截止频率;同时,还能够提高器件的击穿电压,并减小器件的热载流子效应。

部分耗尽异质环栅场效应晶体管阈值电压模型

为抑制短沟道效应和解决载流子传输效率低的问题,提出了部分耗尽异质环栅金属氧化物半导体场效应晶体管(MOSFET)结构(DMSG),并建立了器件的表面电势和阈值电压解析模型。异质环栅由两种具有不同功函数的材料无缝拼接形成,能在沟道中产生电场峰值,降低漏端电场,并屏蔽漏压对最小表面势的影响。通过为沟道耗尽层各区建立柱坐标下电势泊松方程和相应的边界条件方程,采用径向抛物线近似对偏微分方程进行降维和解析求解技术,获得了DMSG结构的解析模型。仿真结果表明,与传统的部分耗尽环栅器件相比,DMSG结构载流子传输效率高,短沟道效应、漏致势垒降低效应和热载流子效应抑制能力强;所建解析模型与数值仿真软件的相对误差小于5%。

复合多晶硅栅LDMOS的特性研究

提出了一种应用于射频领域的复合多晶硅栅LDMOS结构(DMG-LDMOS),并给出了工艺实现方法。此结构采用了栅工程的概念,所设计的栅电极由S-栅和D-栅两块电极并列组成,其中,S-栅采用功函数较高的p+多晶硅;D-栅采用功函数较低的n+多晶硅。MEDICI对n沟道DMG-LDMOS和n沟道普通LDMOS的模拟结果表明,该结构能够提高器件的沟道载流子速度,从而增加器件的跨导值,并且该结构在提高器件击穿电压的同时还能提高器件的截止频率。

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOS-FET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.

蚀刻设备的现状与发展趋势

概述了蚀刻技术与设备的现状,针对32nm技术节点器件制程对蚀刻设备在双重图形蚀刻、高k/金属栅材料、金属硬掩膜及进入后摩尔时代三维封装的通孔硅技术(TSV)方面挑战,介绍了蚀刻设备的发展趋势。

异质双栅结构LDMOS的物理建模和仿真

对一种采用新结构的LDMOS(lateral double diffused metal oxide semiconductor)器件建立了模型.该器件在LDMOS中采用异质双栅(dual material gate,DMG)结构,这样使得该器件(DMG-LDMOS)同时具有LDMOS和DMG MOSFET的特性和优点.给出了DMG-LDMOS中沟道区表面电势和电场的一维表达式,并在此基础上考虑了大驱动电压下引入的沟道载流子速度过冲效应的影响,建立了基于物理的沟道电流模型.最后比较了Medici器件仿真结果和所建立的沟道电流模型,验证了该模型的可用性.