A new current feedback amplifier (CFA) based dual-input differentiator (DID) design with grounded capacitor is presented;its time constant (τo) is independently tunable by a single resistor. The proposed circuit yiel...A new current feedback amplifier (CFA) based dual-input differentiator (DID) design with grounded capacitor is presented;its time constant (τo) is independently tunable by a single resistor. The proposed circuit yields a true DID function with ideal CFA devices. Analysis with nonideal devices having parasitic capacitance (Cp) shows extremely low but finite phase error (θe);suitable design θe could be minimized significantly. The design is practically active-insensitive relative to port mismatch errors (ε) of the active element. An allpass phase shifter circuit implementation is derived with slight modification of the differentiator. Satisfactory experimental results had been verified on typical wave processing and phase-selective filter design applications.展开更多
自动调制识别是现代通信系统中一项重要技术。为提高通信系统对不同调制信号间的识别性能,文中首先探索了包含11类调制信号的公开数据集RML2016.10A上原始同相正交(In-phase and Quadrature,IQ)格式数据和经过数据预处理后的幅度和相位(...自动调制识别是现代通信系统中一项重要技术。为提高通信系统对不同调制信号间的识别性能,文中首先探索了包含11类调制信号的公开数据集RML2016.10A上原始同相正交(In-phase and Quadrature,IQ)格式数据和经过数据预处理后的幅度和相位(Amplitude and Phase,AP)格式数据的差异;随后,依据原始IQ格式数据和AP格式数据在特征提取过程中对局部相关性及时序特征敏感性的差异,设计了针对空间特征提取的SFE-Block模块、针对长期依赖关系提取的TFE-Block模块,以及联合时空特征提取模块STFE-Block,并将前两者的输出特征作为STFE-Block模块输出特征的重要补充进行特征融合,以全连接(Fully Connected)层负责最终分类。实验结果表明,本模型在数据集RML2016.10A上表现良好。当信噪比(Signal to Noise Ratio,SNR)低于-8 dB时,平均识别精度比其他模型提升7%,而SNR在0~18 dB时,平均识别精度比其他模型提高1%~8%,且在SNR为16 dB时,最高识别精度达92.95%。此外,在RML2016.10B数据集上重复了实验以检验模型泛化性,所得结果同样最优,且当SNR为12 dB时,最高识别精度达到93.6%。展开更多
A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk p...A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.展开更多
The objective of this work is the coordinated design of controllers that can enhance damping of power system swings. With presence of flexible AC transmission system （FACTS） device as unified power flow controller ...The objective of this work is the coordinated design of controllers that can enhance damping of power system swings. With presence of flexible AC transmission system （FACTS） device as unified power flow controller （UPFC）, three specific classes of the power system stabilizers （PSSs） have been investigated. The first one is a conventional power system stabilizer （CPSS）; the second one is a dual-input power system stabilizer （dual-input PSS）; and the third one is an accelerating power PSS model （PSS2B）. Dual-input PSS and PSS2B are introduced to maintain the robustness of control performance in a wide range of swing frequency. Uncoordinated PSS and UPFC damping controller may cause unwanted interactions; therefore, the simultaneous coordinated tuning of the controller parameters is needed. The problem of coordi- nated design is formulated as an optimization problem, and particle swarm optimization （PSO） algorithm is employed to search for optimal parameters of controllers. Finally, in a system having a UPFC, comparative analysis of the results obtained from application of the dual-input PSS, PSS2B, and CPSS is presented. The eigenvalue analysis and the time-domain simulation results show that the dual-input PSS ＆ UPFC and the PSS2B ＆ UPFC coordination provide a better performance than the conventional single-input PSS ＆ UPFC coordination. Also, the PSS2B ＆ UPFC coordination has the best performance.展开更多
文摘A new current feedback amplifier (CFA) based dual-input differentiator (DID) design with grounded capacitor is presented;its time constant (τo) is independently tunable by a single resistor. The proposed circuit yields a true DID function with ideal CFA devices. Analysis with nonideal devices having parasitic capacitance (Cp) shows extremely low but finite phase error (θe);suitable design θe could be minimized significantly. The design is practically active-insensitive relative to port mismatch errors (ε) of the active element. An allpass phase shifter circuit implementation is derived with slight modification of the differentiator. Satisfactory experimental results had been verified on typical wave processing and phase-selective filter design applications.
文摘自动调制识别是现代通信系统中一项重要技术。为提高通信系统对不同调制信号间的识别性能,文中首先探索了包含11类调制信号的公开数据集RML2016.10A上原始同相正交(In-phase and Quadrature,IQ)格式数据和经过数据预处理后的幅度和相位(Amplitude and Phase,AP)格式数据的差异;随后,依据原始IQ格式数据和AP格式数据在特征提取过程中对局部相关性及时序特征敏感性的差异,设计了针对空间特征提取的SFE-Block模块、针对长期依赖关系提取的TFE-Block模块,以及联合时空特征提取模块STFE-Block,并将前两者的输出特征作为STFE-Block模块输出特征的重要补充进行特征融合,以全连接(Fully Connected)层负责最终分类。实验结果表明,本模型在数据集RML2016.10A上表现良好。当信噪比(Signal to Noise Ratio,SNR)低于-8 dB时,平均识别精度比其他模型提升7%,而SNR在0~18 dB时,平均识别精度比其他模型提高1%~8%,且在SNR为16 dB时,最高识别精度达92.95%。此外,在RML2016.10B数据集上重复了实验以检验模型泛化性,所得结果同样最优,且当SNR为12 dB时,最高识别精度达到93.6%。
基金Project supported by the National Natural Science Foundation of China(No.60876019)the National S&T Major Project of China(No. 2009ZX0131-002-003-02)+2 种基金the Shanghai Rising-Star Program(No.09QA1400300)the National Scientists and Engineers Service for Enterprise Program,China(No.2009GJC00046)the ASIC State-Key Laboratory Funding,China(No.09MS007)
文摘A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.
文摘The objective of this work is the coordinated design of controllers that can enhance damping of power system swings. With presence of flexible AC transmission system （FACTS） device as unified power flow controller （UPFC）, three specific classes of the power system stabilizers （PSSs） have been investigated. The first one is a conventional power system stabilizer （CPSS）; the second one is a dual-input power system stabilizer （dual-input PSS）; and the third one is an accelerating power PSS model （PSS2B）. Dual-input PSS and PSS2B are introduced to maintain the robustness of control performance in a wide range of swing frequency. Uncoordinated PSS and UPFC damping controller may cause unwanted interactions; therefore, the simultaneous coordinated tuning of the controller parameters is needed. The problem of coordi- nated design is formulated as an optimization problem, and particle swarm optimization （PSO） algorithm is employed to search for optimal parameters of controllers. Finally, in a system having a UPFC, comparative analysis of the results obtained from application of the dual-input PSS, PSS2B, and CPSS is presented. The eigenvalue analysis and the time-domain simulation results show that the dual-input PSS ＆ UPFC and the PSS2B ＆ UPFC coordination provide a better performance than the conventional single-input PSS ＆ UPFC coordination. Also, the PSS2B ＆ UPFC coordination has the best performance.
