A Single Resistor Tunable Grounded Capacitor Dual-Input Differentiator

A new current feedback amplifier (CFA) based dual-input differentiator (DID) design with grounded capacitor is presented;its time constant (τo) is independently tunable by a single resistor. The proposed circuit yields a true DID function with ideal CFA devices. Analysis with nonideal devices having parasitic capacitance (Cp) shows extremely low but finite phase error (θe);suitable design θe could be minimized significantly. The design is practically active-insensitive relative to port mismatch errors (ε) of the active element. An allpass phase shifter circuit implementation is derived with slight modification of the differentiator. Satisfactory experimental results had been verified on typical wave processing and phase-selective filter design applications.

Design of Low Voltage, Low Power (IF) Amplifier Based-On MOSFET Darlington Configuration

This paper presents a different approach of Intermediate Frequency (IF) amplifier using 0.18 μm MIETEC technology channel length of MOSFET Darlington transistors. In contrast to Bipolar conventional Darlingtonpair, a MOSFET Darlington configuration is employed to reduce supply voltage (VDD) and DC consumption power (Pc). The frequency response parameters of the proposed design such as bandwidth, gain bandwidth product, input/output noises and noise figure (NF) are improved in proposed (IF) amplifier. Moreover, a dual-input and dual-output (DIDO) IF amplifier constructed from two symmetrical single input and single output (SISO) (IF) amplifier is proposed too. The idea is to achieve improved bandwidth, and flat response, because these parameters are very important in high frequency applications. Simulation results that obtained by P-SPICE program are 1.2 GHz Bandwidth (BW), 3.4 GHz (gain bandwidth product), 0.5 mW DC consumption power (Pc) and the low total output noise is 12 nV with 1.2 V single supply voltage.

A New Precision Peak Detector/Full-Wave Rectifier

A new precision peak detector/full-wave rectifier of input sinusoidal signals, based on usage of dual-output current conveyors, is presented in this paper. The circuit gives a DC output voltage that is the peak input voltage over a wide frequency range, with a very low ripple voltage and low harmonic distortion. The proposed circuits use an all-pass filter as a 90° phase shifter of the processed input signal. To verify the theoretical analysis, the circuit SPICE simulations results have also been included, showing good agreement with the theory. Inherently, the circuit is well suited for IC implementation.

Switching response of dual-output Mach–Zehnder modulator in channel-interleaved photonic analog-to-digital converter

This Letter theoretically and experimentally studies the response of photonic switching in a channel-interleaved photonic analog-to-digital converter(PADC) with high sampling rate and wide input frequency range. A figure of merit(FoM) is introduced to evaluate the switching response of the PADC when a dual-output Mach–Zehnder modulator(MZM) serves as the photonic switch to parallelize the sampled pulse train into two channels. After the optimization of the FoM and utilization of the channel-mismatch compensation algorithm,the system bandwidth of PADC is expanded and the signal-to-distortion ratio is enhanced.

A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC

A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.

Improving power system dynamic performance using attuned design of dual-input PSS and UPFC PSD controller

The objective of this work is the coordinated design of controllers that can enhance damping of power system swings. With presence of flexible AC transmission system （FACTS） device as unified power flow controller （UPFC）, three specific classes of the power system stabilizers （PSSs） have been investigated. The first one is a conventional power system stabilizer （CPSS）; the second one is a dual-input power system stabilizer （dual-input PSS）; and the third one is an accelerating power PSS model （PSS2B）. Dual-input PSS and PSS2B are introduced to maintain the robustness of control performance in a wide range of swing frequency. Uncoordinated PSS and UPFC damping controller may cause unwanted interactions; therefore, the simultaneous coordinated tuning of the controller parameters is needed. The problem of coordi- nated design is formulated as an optimization problem, and particle swarm optimization （PSO） algorithm is employed to search for optimal parameters of controllers. Finally, in a system having a UPFC, comparative analysis of the results obtained from application of the dual-input PSS, PSS2B, and CPSS is presented. The eigenvalue analysis and the time-domain simulation results show that the dual-input PSS ＆ UPFC and the PSS2B ＆ UPFC coordination provide a better performance than the conventional single-input PSS ＆ UPFC coordination. Also, the PSS2B ＆ UPFC coordination has the best performance.

Monolithic quasi-sliding-mode controller for SIDO buck converter with a self-adaptive free-wheeling current level

An analog implementation of a novel fixed-frequency quasi-sliding-mode controller for single-inductor dual-output（SIDO） buck converter in pseudo-continuous conduction mode（PCCM） with a self-adaptive freewheeling current level（SFCL） is presented.Both small and large signal variations around the operation point are considered to achieve better transient response so as to reduce the cross-regulation of this SIDO buck converter.Moreover,an internal integral loop is added to suppress the steady-state regulation error introduced by conventional PWM-based sliding mode controllers.Instead of keeping it as a constant value,the free-wheeling current level varies according to the load condition to maintain high power efficiency and less cross-regulation at the same time.To verify the feasibility of the proposed controller,an SIDO buck converter with two regulated output voltages,1.8 V and 3.3 V,is designed and fabricated in HEJIAN 0.35 m CMOS process.Simulation and experiment results show that the transient time of this SIDO buck converter drops to 10 s while the cross-regulation is reduced to 0.057 mV/mA,when its first load changes from 50 to 100 mA.

Developing a Super-lift Luo-converter with Integration of Buck Converters for Electric Vehicle Applications

In this paper,a DC-DC multi-port converter is introduced by integrating a super-lift and a buck converter(SLBC).The proposed single-input dual-output(SIDO)converter has conventional positive output voltage super-lift advantages while simultaneously generating a step・up voltage by Luo・converter and a step-down voltage by the buck converter.In this structure,without utilizing electromagnetic components to generate a dual output,the ripple in output voltages is kept low.Meanwhile,the introduced SLBC has a simple structure and an appropriate control method providing a wide range of output voltages.Besides,to illustrate the advantages of the proposed SIDO converter,a comparison with other similar configurations is carried out.Also,simulation and experiment results indicate a considerable reduction in conduction losses compared to other SIDO converters in the same situations.The operation accuracy of SLBC is validated by performing several simulations in PSCAD/EMTDC software and testing a 150W prototype in the laboratory.