s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure re...s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.展开更多
An ＂automatic power down＂ method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode. Implemented with the TSMC 0.25vm mi...An ＂automatic power down＂ method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode. Implemented with the TSMC 0.25vm mixed-sig- nal CMOS process,the 4/5 MOS current mode logic prescaler is designed with this automatic power down technique. The simulation results show that the new 4/5 prescaler is immune to the ＂wake-up＂ issue and thereby retains the same maxi- mum operating frequency as the conventional prescaler. An integer-N divider with this proposed prescaler and with the di- vision ratio 66/67 is manufactured,and it is estimated to save more than 20% of the power compared with the conventional 4/5 prescaler.展开更多
A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed t...A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.展开更多
This paper describes a novel divide-by-32/33 dual-modulus prescaler （DMP）. Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPS...This paper describes a novel divide-by-32/33 dual-modulus prescaler （DMP）. Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18μm CMOS process of SMIC. The measured results show that the DMP＇s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 x 30 #m2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications.展开更多
An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods ...An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.展开更多
A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 presc...A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.展开更多
A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperatur...A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperature and power supply.The value of the charge-pump current can be changed by switches,which are controlled by external signals.Thus the performance of the PLL,such as loop bandwidth,can be changed with the change of the charge-pump current.The loop filter initialization circuit can speed up the PLL when the power is on.A multi-modulus prescaler is used to fulfill the frequency synthesis.The circuit is designed using 0.18μm,1.8V,1P6M standard digital CMOS process.展开更多
文摘s:A divide- by- 12 8/ 12 9or6 4/ 6 5 dual- modulus prescaler based on new optimized structure and dynam ic circuit technique im plem ented in 0 .2 5 μm CMOS digital technology is described.New optimized structure reduces the propagation delay and has higher operating speed.Based on this structure,an im proved D- flip- flop(DFF) using dynam ic circuit technique is proposed.A prototype is fabricated and the measured results show that this prescaler works well in gigahertz frequency range and consumes only35 m W(including three power- hungry output buffers) when the input frequency is2 .5 GHz and the power supply voltage is2 .5 V.Due to its excellent perform ance,the prescaler could be applied to many RF system s.
文摘An ＂automatic power down＂ method is introduced to design a 4/5 prescaler,with the characteristic of making one of its D-flip-flops power down when it operates in divide-by-4 mode. Implemented with the TSMC 0.25vm mixed-sig- nal CMOS process,the 4/5 MOS current mode logic prescaler is designed with this automatic power down technique. The simulation results show that the new 4/5 prescaler is immune to the ＂wake-up＂ issue and thereby retains the same maxi- mum operating frequency as the conventional prescaler. An integer-N divider with this proposed prescaler and with the di- vision ratio 66/67 is manufactured,and it is estimated to save more than 20% of the power compared with the conventional 4/5 prescaler.
文摘A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.
文摘This paper describes a novel divide-by-32/33 dual-modulus prescaler （DMP）. Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18μm CMOS process of SMIC. The measured results show that the DMP＇s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 x 30 #m2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications.
文摘An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.
文摘A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.
文摘A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperature and power supply.The value of the charge-pump current can be changed by switches,which are controlled by external signals.Thus the performance of the PLL,such as loop bandwidth,can be changed with the change of the charge-pump current.The loop filter initialization circuit can speed up the PLL when the power is on.A multi-modulus prescaler is used to fulfill the frequency synthesis.The circuit is designed using 0.18μm,1.8V,1P6M standard digital CMOS process.
