An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measure-ment.To improve the magnetic sensitivity and to obtain low offset,a fully symmetric vertical Hall device(F...An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measure-ment.To improve the magnetic sensitivity and to obtain low offset,a fully symmetric vertical Hall device(FSVHD)has been op-timized with a minimum size design.A new four-phase spinning current modulation associated with a correlated double sampling(CDS)demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage.The vertical Hall sensor chip has been manufactured in a 0.18μm low-voltage CMOS technology and it occu-pies an area of 1.54 mm2.The experimental results show in the magnetic field range from-200 to 200 mT,the entire vertical Hall sensor performs with the linearity of 99.9%and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60μT.Meanwhile,it consumes 4.5 mW at a 3.3 V supply voltage.The proposed vertical Hall sensor is very suitable for the low-cost sys-tem-on-chip(SOC)implementation of 2D or 3D magnetic microsystems.展开更多
基金the National Natural Science Foundation of China(Nos.61871231,62171233)the Natural Science Foundation of Jiangsu Province,China(No.BK20181390)+1 种基金the Key Research&Development Plan of Jiangsu Province,China(No.BE2019741)the Agricultural Science and Technology Independent Innovation Foundation of Jiangsu Province,China(No.CX(21)3062).
文摘An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measure-ment.To improve the magnetic sensitivity and to obtain low offset,a fully symmetric vertical Hall device(FSVHD)has been op-timized with a minimum size design.A new four-phase spinning current modulation associated with a correlated double sampling(CDS)demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage.The vertical Hall sensor chip has been manufactured in a 0.18μm low-voltage CMOS technology and it occu-pies an area of 1.54 mm2.The experimental results show in the magnetic field range from-200 to 200 mT,the entire vertical Hall sensor performs with the linearity of 99.9%and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60μT.Meanwhile,it consumes 4.5 mW at a 3.3 V supply voltage.The proposed vertical Hall sensor is very suitable for the low-cost sys-tem-on-chip(SOC)implementation of 2D or 3D magnetic microsystems.
