Time-varying frequency selective attenuation and colored noises are unfavorable characteristics of power line communication(PLC) channels of the low voltage networks.To overcome these disadvantages,a novel real-time d...Time-varying frequency selective attenuation and colored noises are unfavorable characteristics of power line communication(PLC) channels of the low voltage networks.To overcome these disadvantages,a novel real-time dynamic spectrum management(DSM) algorithm in orthogonal frequency division multiplexing(OFDM)-based high-speed narrow-band power line communication(HNPLC) systems is proposed,and the corresponding FPGA circuit is designed and realized.Performance of the proposed DSM is validated with a large amount of network experiments under practical PLC circumstance.As the noise in each narrow subcarrier is approximately Gaussian,the proposed DSM adopts the BER/SER expression formulized via the AWGN channel to provide a handy and universal strategy for power allocation.The real-time requirement is guaranteed by choosing subcarriers in group and employing the same modulation scheme within each transmission.These measures are suitable for any modulation scheme no matter the system criterion is to maximize data rate or minimize power/BER.Algorithm design and hardware implementation of the proposed DSM are given with some flexible and efficient conversions.The DSM circuit is carried out with Xilinx KC705.Simulation and practical experiments validate that the proposed real-time DSM significantly improves system performance.展开更多
Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of te...Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.展开更多
Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of com...Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of computational systems is changing with the advancement in technology.Due to shrinking and smaller chip size power densities onchip are increasing rapidly that increasing chip temperature in multi-core embedded technologies.The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor(CMOS)circuits because high on-chip temperature adversely affects the life span of the chip.In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first(EA-EDF)scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip(SOC).Dynamic power management(DPM)enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration.Task migration avoids peak temperature values in the multicore system.High utilization factor(ui)on central processing unit(CPU)core consumes more energy and increases the temperature on-chip.Our technique switches the core bymigrating such task to a core that has less temperature and is in a low power state.The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core.The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works.The simulation results show the improvement in performance by optimizing 4.8%on u_(i) 9%,16%,23%and 25%at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.展开更多
虚拟电厂(virtual power plant,VPP)是一种新型运行模式,通过有效聚合电网中大量需求侧资源并制定有效的动态聚合调控策略,实现电网不同时空的功率互补,提高电网调控的灵活性和系统的经济性。从电网调度角度分析了典型电网需求响应行为...虚拟电厂(virtual power plant,VPP)是一种新型运行模式,通过有效聚合电网中大量需求侧资源并制定有效的动态聚合调控策略,实现电网不同时空的功率互补,提高电网调控的灵活性和系统的经济性。从电网调度角度分析了典型电网需求响应行为特性,提出了需求响应能力指标和虚拟电厂分类聚合方法,构建了多源虚拟电厂调控模型,以其结果支撑虚拟电厂响应资源的分层分区互补调控。最后,以某园区为案例,分析了虚拟电厂调控策略的合理性和多源虚拟电厂调控的科学性。结果表明,整体动态调控策略可以引导虚拟电厂科学合理地发挥需求响应价值,促进电网负荷平稳和系统安全稳定运行。展开更多
基金Supported by the Tsinghua University International Science and Technology Cooperation Project(No.20133000197,20123000148)
文摘Time-varying frequency selective attenuation and colored noises are unfavorable characteristics of power line communication(PLC) channels of the low voltage networks.To overcome these disadvantages,a novel real-time dynamic spectrum management(DSM) algorithm in orthogonal frequency division multiplexing(OFDM)-based high-speed narrow-band power line communication(HNPLC) systems is proposed,and the corresponding FPGA circuit is designed and realized.Performance of the proposed DSM is validated with a large amount of network experiments under practical PLC circumstance.As the noise in each narrow subcarrier is approximately Gaussian,the proposed DSM adopts the BER/SER expression formulized via the AWGN channel to provide a handy and universal strategy for power allocation.The real-time requirement is guaranteed by choosing subcarriers in group and employing the same modulation scheme within each transmission.These measures are suitable for any modulation scheme no matter the system criterion is to maximize data rate or minimize power/BER.Algorithm design and hardware implementation of the proposed DSM are given with some flexible and efficient conversions.The DSM circuit is carried out with Xilinx KC705.Simulation and practical experiments validate that the proposed real-time DSM significantly improves system performance.
文摘Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.
文摘Minimizing the energy consumption to increase the life span and performance of multiprocessor system on chip(MPSoC)has become an integral chip design issue for multiprocessor systems.The performance measurement of computational systems is changing with the advancement in technology.Due to shrinking and smaller chip size power densities onchip are increasing rapidly that increasing chip temperature in multi-core embedded technologies.The operating speed of the device decreases when power consumption reaches a threshold that causes a delay in complementary metal oxide semiconductor(CMOS)circuits because high on-chip temperature adversely affects the life span of the chip.In this paper an energy-aware dynamic power management technique based on energy aware earliest deadline first(EA-EDF)scheduling is proposed for improving the performance and reliability by reducing energy and power consumption in the system on chip(SOC).Dynamic power management(DPM)enables MPSOC to reduce power and energy consumption by adopting a suitable core configuration for task migration.Task migration avoids peak temperature values in the multicore system.High utilization factor(ui)on central processing unit(CPU)core consumes more energy and increases the temperature on-chip.Our technique switches the core bymigrating such task to a core that has less temperature and is in a low power state.The proposed EA-EDF scheduling technique migrates load on different cores to attain stability in temperature among multiple cores of the CPU and optimized the duration of the idle and sleep periods to enable the low-temperature core.The effectiveness of the EA-EDF approach reduces the utilization and energy consumption compared to other existing methods and works.The simulation results show the improvement in performance by optimizing 4.8%on u_(i) 9%,16%,23%and 25%at 520 MHz operating frequency as compared to other energy-aware techniques for MPSoCs when the least number of tasks is in running state and can schedule more tasks to make an energy-efficient processor by controlling and managing the energy consumption of MPSoC.
文摘虚拟电厂(virtual power plant,VPP)是一种新型运行模式,通过有效聚合电网中大量需求侧资源并制定有效的动态聚合调控策略,实现电网不同时空的功率互补,提高电网调控的灵活性和系统的经济性。从电网调度角度分析了典型电网需求响应行为特性,提出了需求响应能力指标和虚拟电厂分类聚合方法,构建了多源虚拟电厂调控模型,以其结果支撑虚拟电厂响应资源的分层分区互补调控。最后,以某园区为案例,分析了虚拟电厂调控策略的合理性和多源虚拟电厂调控的科学性。结果表明,整体动态调控策略可以引导虚拟电厂科学合理地发挥需求响应价值,促进电网负荷平稳和系统安全稳定运行。
