Temperature-Based Fan Speed Optimization Strategy

As energy efficiency and indoor comfort increasingly become key standards in modern residential and office environments,research on intelligent fan speed control systems has become particularly important.This study aims to develop a temperature-feedback-based fan speed optimization strategy to achieve higher energy efficiency and user comfort.Firstly,by analyzing existing fan speed control technologies,their main limitations are identified,such as the inability to achieve smooth speed transitions.To address this issue,a BP-PID speed control algorithm is designed,which dynamically adjusts fan speed based on indoor temperature changes.Experimental validation demonstrates that the designed system can achieve smooth speed transitions compared to traditional fan systems while maintaining stable indoor temperatures.Furthermore,the real-time responsiveness of the system is crucial for enhancing user comfort.Our research not only demonstrates the feasibility of temperature-based fan speed optimization strategies in both theory and practice but also provides valuable insights for energy management in future smart home environments.Ultimately,this research outcome will facilitate the development of smart home systems and have a positive impact on environmental sustainability.

Experimental study on dynamic load magnification factor for ballastless track-subgrade of high-speed railway

The magnitude of dynamic load produced by high-speed trains depends on many factors,of which train speed is the most critical one.However,it is quite difficult to determine the effect of train speed on dynamic load using the theoretical methods due to the complexity of the interaction between vehicle and track-subgrade.Thus large-scale model test has gradually become an important approach for studying dynamic responses of ballastless track-subgrade of high-speed railway.In this study,a full-scale model of ballastless track-subgrade was constructed in accordance with the design and construction standards for Shanghai-Nanjing intercity high-speed railway line firstly.Then,the dynamic strain of slab and the dynamic earth pressure of subgrade were measured by conducting single wheel axle excitation test.In addition,the relationship between the dynamic load magnification factor（DLF） and the train speed was obtained.Finally,the DLF of track-subgrade under different train speeds was proposed,similar to that given by German Railway Standard.

MODELING AND IMPLEMENTATION OF SPEED GOVERNOR FOR THE HYBRID ELECTRIC VEHICLE ENGINE

A speed control analysis for an in-line gasoline fueled internal combustion （IC） engine is presented for the purpose of alleviation of high frequency oscillations in engine revolutions. A dynamic cylinder-by-cylinder model is proposed, base on slider-crank mechanism, which is extended to develop a digital governor providing a high fidelity estimation of rotary speed oscillation for hybrid vehicle engines. A modified PID controller that P and I gain is placed in feedback path is also described for hybrid electric vehicle （HEV） engine speed regulation, By comparison between measured and estimated signals, it is demonstrated that a good agreement has been achieved and the governor behaves an excellent damping speed ripple.

Optimal control strategy for energy saving in trains under the four-aspect fixed autoblock system

This paper deals with both the leading train and the following train in a train tracking under a four-aspect fixed autoblock system in order to study the optimum operating strategy for energy saving. After analyzing the working principle of the four-aspect fixed autoblock system, an energy-saving control model is created based on the dynamics equation of the Wains. In addition to safety, energy consumption and time error are the main concerns of the model. Based on this model, dynamic speed constraints of the following train are proposed, defined by the leading gain dynamically. At the same time, the static speed constraints defined by the line conditions are also taken into account. The parallel genetic algorithm is used to search the optimum operating strategy. In order to simplify the solving process, the external punishment function is adopted to transform this problem with constraints to the one without constraints. By using the real number coding and the strategy of dividing ramps into three parts, the convergence of GA is accelerated and the length of chromosomes is shortened. The simulation result from a four-aspect fixed autoblock system simulation platform shows that the method can reduce the energy consumption effectively in the premise of ensuring safety and punctuality.

Innovated Inertia Control of DFIG with Dynamic Rotor Speed Recovery

High wind power penetration(WPP)is challenging system frequency stability.As a countermeasure,virtual inertia controls are introduced,utilizing kinetic energy(KE)stored in wind turbine generators(WTGs)for frequency regulation.Without restoration,generation efficiency of WTGs will be degraded after inertia contribution.To counter this issue,we propose an inertia control scheme of a doubly fed induction generator(DFIG),aiming at achieving dynamic inertia recovery regarding both KE and DC link energy.An asymmetrical droop control,referred to as the rate of change of frequency(RoCoF),is proposed for KE management.The upper boundary of droop gain is extended to give full play to converters and is revised,considering the system frequency state,to counter positive feedback issues induced by reversible gain regulation,which is restricted by KE to ensure stable operations as well.The inertial DC energy needed to cooperate with KE control regarding countering small fluctuations,is improved with an orderly recovery behavior.Case studies are conducted under dynamic wind conditions and the results indicate that with our proposed scheme,the ability of dynamic inertia recovery can be obtained,bringing DFIG higher generation efficiency and more adequate operation margin for sustained regulation.Essentially,the inertial frequency response and fluctuation suppression ability is well maintained.

A 2.5 GS/s 14-bit D/A converter with 8 to 1 MUX

A 2.5 GS/s 14-bit D/A converter（DAC） with 8 to 1 MUX is presented. This 14-bit DAC uses a ＂5＋9＂segment PMOS current-steering architecture. A bias circuit which ensures the PMOS current source obtains a larger output impedance under every PVT（process, source voltage and temperature） corner is also presented. The8 to 1 MUX has a 3 stage structure, and a proper timing sequence is designed to ensure reliable data synthesis. A DEM function which is merged with a ＂5-31＂decoder is used to improve the DAC＇s dynamic performance. This DAC is embedded in a 2.5 GHz direct digital frequency synthesizer（DDS） chip, and is implemented in a 0.18 m CMOS technology, occupies 4.86 2. 28 mm-2 including bond pads（DAC only）, and the measured performance is SFDR 〉 40 d B（with and without DEM） for output signal frequency up to 1 GHz. Compared with other present published DACs with a non-analog-resample structure（means return-to-zero or quad-switch structure is unutilized）,this paper DAC＇s clock frequency（2.5 GHz） and higher output frequency SFDR（〉 40 d B, up to 1 GHz） has some competition.