Ionic effects on the transport characteristics of nanowire-based FETs in a liquid environment

For the development of ultra-sensitive electrical bio/chemical sensors based on nanowire field effect transistors （FETs）, the influence of the ions in the solution on the electron transport has to be understood. For this purpose we establish a simulation platform for nanowire FETs in the liquid environment by implementing the modified Poisson-Boltzmann model into Landauer transport theory. We investigate the changes of the electric potential and the transport characteristics due to the ions. The reduction of sensitivity of the sensors due to the screening effect from the electrolyte could be successfully reproduced. We also fabricated silicon nanowire Schottky-barrier FETs and our model could capture the observed reduction of the current with increasing ionic concentration. This shows that our simulation platform can be used to interpret ongoing experiments, to design nanowire FETs, and it also gives insight into controversial issues such as whether ions in the buffer solution affect the transport characteristics or not.

Wrinkle-free graphene with spatially uniform electrical properties grown on hot-pressed copper

The chemical vapor deposition （CVD） of graphene on Cu substrates enables the fabrication of large-area monolayer graphene on desired substrates. However, during the transfer of the synthesized graphene, topographic defects are unavoidably formed along the Cu grain boundaries, degrading the electrical properties of graphene and increasing the device-to-device variability. Here, we introduce a method of hot-pressing as a surface pre-treatment to improve the thermal stability of Cu thin film for the suppression of grain boundary grooving. The flattened Cu thin film maintains its smooth surface even after the subsequent high temperature CVD process necessary for graphene growth, and the formation of graphene without wrinkles is realized. Graphene field effect transistors （FETs） fabricated using the graphene synthesized on hot-pressed Cu thin film exhibit superior field effect mobility and significantly reduced device-to-device variation.

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.