Special Issue on Electromechanical Coupling Design for Electronic Equipment

With the development of electronic equipment to high accuracy, high density, high frequency, and atrocious ser- vice environment, the functional surface in this type of equipment has increasingly serious problems,

SIMULATION IN THERMAL DESIGN FOR ELECTRONIC CONTROL UNIT OF ELECTRONIC UNIT PUMP

The high working junction temperature of power component is the most common reason of its failure. So the thermal design is of vital importance in electronic control unit （ECU） design. By means of circuit simulation, the thermal design of ECU for electronic unit pump （EUP） fuel system is applied. The power dissipation model of each power component in the ECU is created and simulated. According to the analyses of simulation results, the factors which affect the power dissipation of components are analyzed. Then the ways for reducing the power dissipation of power components are carried out. The power dissipation of power components at different engine state is calculated and analyzed. The maximal power dissipation of each power component in all possible engine state is also carried out based on these simulations. A cooling system is designed based on these studies. The tests show that the maximum total power dissipation of ECU drops from 43.2 W to 33.84 W after these simulations and optimizations. These applications of simulations in thermal design of ECU can greatly increase the quality of the design, save the design cost and shorten design time

Method of reliability tolerance design based on EDA technology and its application on DC hybrid contactor

Tolerance design, including tolerance analysis and distribution, is an important part of the electronic system’s reli- ability design. The traditional design needs to construct mathematic model of material circuit, which involves large amount of workload and lacks of practicability. This paper discusses the basic theory of electronic system’s reliability tolerance design and presents a new design method based on EDA (Electronic Design Automatic) software. This method has been validated through the application research on reliability tolerance design of the DC hybrid contactor’s control circuit.

STRUCTURE DESIGN OF THE BEIJING SPECTROMETERⅢBEAM PIPE

The Beijing spectrometer Ⅲ （BESⅢ） beam pipe is in the center of the BESⅢ, which is the detector of the upgrade project of Beijing electron and positron collider （BEPC Ⅱ）. Electrons and positrons collide in the BESⅢ beam pipe. According to the demands of the BEPC Ⅱ, a key program of Chinese Academy of Sciences, the BESⅢ beam pipe is designed based on the finite elements analysis. The BESIII beam pipe is installed in the inner cylinder of the BESⅢ drift chamber. As a vacuum tube, the BESIII beam pipe is designed as 1 000 mm in length, 63 mm in inner diameter and 114 mm in outer diameter, respectively. The BESIII beam pipe consists of a central beryllium pipe cooled by EDM-1, the oil No.1 for electric discharge machining, and two extended copper pipes cooled by deionized water （DW）. The three parts are jointed by vacuum welding. Factors taken into account in the design are as follows. ① The wall thickness of the central beryllium pipe should be designed as small as possible to reduce the multi-scattering and improve the particle momentum resolution. And the wall thickness of the extended copper pipe should be designed as large as possible to protect the detectors from the backgrounds. ②The BESⅢ beam pipe must be sufficiently cooled to avoid the damage and prevents its influence to the BESⅢ drift chamber （DC） operation. The inner surface temperature of the DC inner cylinder must be maintained at 293±2 K. ③ The magnetic permeability of the materials used in the BESⅢ beam pipe must be less than 1.05 H/m to avoid large magnetic field distortions. ④ The static pressure of the vacuum chamber of the BESⅢ beam pipe must be less than 800 μPa. The simulating results show that the designed structure of the BESⅢ beam pipe satisfies the requirements mentioned above. The structure design scheme is evaluated and adonted hv the headouarters of BEPCⅡ.

AN ANT COLONY ALGORITHM FOR MINIMUM UNSATISFIABLE CORE EXTRACTION

Explaining the causes of infeasibility of Boolean formulas has many practical applications in electronic design automation and formal verification of hardware.Furthermore,a minimum explanation of infeasibility that excludes all irrelevant information is generally of interest.A smallest-cardinality unsatisfiable subset called a minimum unsatisfiable core can provide a succinct explanation of infea-sibility and is valuable for applications.However,little attention has been concentrated on extraction of minimum unsatisfiable core.In this paper,the relationship between maximal satisfiability and mini-mum unsatisfiability is presented and proved,then an efficient ant colony algorithm is proposed to derive an exact or nearly exact minimum unsatisfiable core based on the relationship.Finally,ex-perimental results on practical benchmarks compared with the best known approach are reported,and the results show that the ant colony algorithm strongly outperforms the best previous algorithm.

Electromagnetic Simulation with 3D FEM for Design Automation in 5G Era

Electromagnetic simulation and electronic design automation(EDA)play an important role in the design of 5G antennas and radio chips.The simulation challenges include electromagnetic effects and long simulation time and this paper focuses on simulation software based on finite-element method(FEM).The state-of-the-art EDA software using novel computational techniques based on FEM can not only accelerate numerical analysis,but also enable optimization,sensitivity analysis and interactive design tuning based on rigorous electromagnetic model of a device.Several new techniques that help to mitigate the most challenging issues related to FEM based simulation are highlighted.In particular,methods for fast frequency sweep,mesh morphing and surrogate models for efficient optimization and manual design tuning are briefly described,and their efficiency is illustrated on examples involving a 5G multiple-input multiple-output(MIMO)antenna and filter.It is demonstrated that these new computational techniques enable significant reduction of time needed for design closure with the acceleration rates as large as tens or even over one hundred.

DYNAMIC LABELING BASED FPGA DELAY OPTIMIZATION ALGORITHM

DAG-MAP is an FPGA technology mapping algorithm for delay optimization and the labeling phase is the algorithm’s kernel. This paper studied the labeling phase and presented an improved labeling method. It is shown through the experimental results on MCNC benchmarks that the improved method is more effective than the original method while the computation time is almost the same.

An Intelligent Design of Electron Lens System

At present, the main work of electron optical system CAD is solving equations and calculating mumerical values. However, the design perhaps needs more inference and expertise than numerical calculations because the structure of electron lens system is complicated. In this paper, a primary expert system is applied to design the electron lens system intelligently. This expert system is combined with SEU-3D program which is used to simulate the electron optical system to optimize the electron lens systems. In spite of this, the expert system which is established in this paper can also be used to diagnose the electron lens system. Although the knowledge base is small and rules are not abundant, this paper has used this system to obtain some very useful results. The initial success with this system suggests that further work need to be done whether more rules and knowledge will be added to extend the ability of expert system.

Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication

Matrix-vector multiplication is the key operation for many computationally intensive algorithms. The emerging metal oxide resistive switching random access memory （RRAM） device and RRAM crossbar array have demonstrated a promising hardware realization of the analog matrix-vector multiplication with ultra-high energy efficiency. In this paper, we analyze the impact of both device level and circuit level non-ideal factors, including the nonlinear current-voltage relationship of RRAM devices, the variation of device fabrication and write operation, and the interconnect resistance as well as other crossbar array parameters. On top of that, we propose a technological exploration flow for device parameter configuration to overcome the impact of non-ideal factors and achieve a better trade-off among performance, energy, and reliability for each specific application. Our simulation results of a support vector machine （SVM） and Mixed National Institute of Standards and Technology （MNIST） pattern recognition dataset show that RRAM crossbar array based SVM is robust to input signal fluctuation but sensitive to tunneling gap deviation. A further resistance resolution test presents that a 6-bit RRAM device is able to realize a recognition accuracy around 90%, indicating the physical feasibility of RRAM crossbar array based SVM. In addition, the proposed technological exploration flow is able to achieve 10.98% improvement of recognition accuracy on the MNIST dataset and 26.4% energy savings compared with previous work. Experimental results also show that more than 84.4% power saving can be achieved at the cost of little accuracy reduction.

SRAM-Based FPGA Systems for Safety-Critical Applications： A Survey on Design Standards and Proposed Methodologies

As the ASIC design cost becomes affordable only for very large-scale productions, the FPGA technology is currently becoming the leading technology for those applications that require a small-scale production. FPGAs can be considered as a technology crossing between hardware and software. Only a small-number of standards for the design of safety-critical systems give guidelines and recommendations that take the peculiarities of the FPGA technology into consideration. The main contribution of this paper is an overview of the existing design standards that regulate the design and verification of FPCA-based systems in safety-critical application fields. Moreover, the paper proposes a survey of significant published research proposals and existing industrial guidelines about the topic, and collects and reports about some lessons learned from industrial and research projects involving the use of FPGA devices.

Integrating advanced reasoning into a SAT solver

In this paper, we present a SAT solver based on the combination of DPLL (Davis Putnam Logemann and Loveland) algorithm and Failed Literal Detection (FLD), one of the advanced reasoning techniques. We propose a Dynamic Filtering method that consists of two restriction rules for FLD: internal and external filtering. The method reduces the number of tested literals in FLD and its computational time while maintaining the ability to find most of the failed literals in each decision level. Unlike the pre-defined criteria, literals are removed dynamically in our approach. In this way, our FLD can adapt itself to different real-life benchmarks. Many useless tests are therefore avoided and as a consequence it makes FLD fast. Some other static restrictions are also added to further improve the efficiency of FLD. Experiments show that our optimized FLD is much more efficient than other advanced reasoning techniques.

New Multipole Method for 3-D Capacitance Extraction

This paper describes an efficient improvement of the multipole accelerated boundary element method for 3-D capacitance extraction. The overall relations between the positions of 2-D boundary elements are considered instead of only the relations between the center-points of the elements, and a new method of cube partitioning is introduced. Numerical results are presented to demonstrate that the method is accurate and has nearly linear computational growth as O(n), where n is the number of panels/boundary elements. The proposed method is more accurate and much faster than Fastcap.

Pulse control of frequency and width for a real-time independently adjustable laser source

A set of semiconductor laser pulse seed sources based on an embedded chip is proposed.The greatest feature is that the optical pulse frequency and width can be independently adjusted in real time.The pulse seed sources can be switched independently and online from the gain-switched mode to the quasi-continuous wave mode to obtain optimal optical parameters for specific applications.To explore the physical mechanism of the semiconductor laser source,the rate equation that describes the carrier-photon transient change in a semiconductor laser cavity is numerically derived and solved.Subsequently,problems that need to be considered while designing the drive circuit are identified.The system evaluation indicates that the optical pulse frequency adjustment range is 250 Hz to 42 MHz,and the narrowest optical pulse output width is 80 ps.The pulse seed source can drive semiconductor lasers with different central wavelengths(1064,1550,and 1970 nm),and can also simultaneously drive two semiconductor lasers and output dual-band optical pulses.It can be used as a seed source for general high-power optical systems,and exhibits good application value and extensive market prospects.