Effect and mechanism of on-chip electrostatic discharge protection circuit under fast rising time electromagnetic pulse

The electrostatic discharge(ESD)protection circuit widely exists in the input and output ports of CMOS digital circuits,and fast rising time electromagnetic pulse(FREMP)coupled into the device not only interacts with the CMOS circuit,but also acts on the protection circuit.This paper establishes a model of on-chip CMOS electrostatic discharge protection circuit and selects square pulse as the FREMP signals.Based on multiple physical parameter models,it depicts the distribution of the lattice temperature,current density,and electric field intensity inside the device.At the same time,this paper explores the changes of the internal devices in the circuit under the injection of fast rising time electromagnetic pulse and describes the relationship between the damage amplitude threshold and the pulse width.The results show that the ESD protection circuit has potential damage risk,and the injection of FREMP leads to irreversible heat loss inside the circuit.In addition,pulse signals with different attributes will change the damage threshold of the circuit.These results provide an important reference for further evaluation of the influence of electromagnetic environment on the chip,which is helpful to carry out the reliability enhancement research of ESD protection circuit.

Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.

A novel diode string triggered gated-Pi N junction device for electrostatic discharge protection in 65-nm CMOS technology

A novel diode string-triggered gated-Pi N junction device, which is fabricated in a standard 65-nm complementary metal-oxide semiconductor（CMOS） technology, is proposed in this paper. An embedded gated-Pi N junction structure is employed to reduce the diode string leakage current to 13 n A/μm in a temperature range from 25°C to 85°C. To provide the effective electrostatic discharge（ESD） protection in multi-voltage power supply, the triggering voltage of the novel device can be adjusted through redistributing parasitic resistance instead of changing the stacked diode number.

Emerging Challenges in ESD Protection for RF ICs in CMOS

On-chip electrostatic discharge （ESD） protection design has become an emerging challenge for radio-frequency （RF） integrated circuits （IC） design as IC technologies migrate into the very-deep-sub-micron （VDSM） regime and RF ICs move into multi-GHz operations. The key problem originates from the complex interaction between the ESD protection circuitry and the core RF IC circuit under protection. This paper discusses the recent development in RF ESD protection research and design,outlining emerging challenges, new design methods,and novel RF ESD protection solutions.

Study on electrostatic discharge(ESD)characteristics of ultra-thin dielectric film

Electrostatic discharge(ESD)event usually destroys the electrical properties of dielectric films,resulting in product failure.In this work,the breakdown characteristic of machine mode(MM)ESD on three different nano size films of head gimble assemble are obtained experimentally.The breakdown voltage and thickness parameters show a positive proportional relationship,but they are generally very low and have large discrete characteristics(~30%).The maximum and minimum breakdown voltages of the tested samples are 1.08 V and 0.46 V,which are far lower than the requirement of the current standard(25 V).In addition,the judgment criterion of product damage is given,and the relationship between discharge voltage polarity,initial resistance and breakdown voltage is studied.Finally,the theoretical analysis of the breakdown characteristic law has been given.

Structure-dependent behaviors of diode-triggered silicon controlled rectifier under electrostatic discharge stress

The comprehensive understanding of the structure-dependent electrostatic discharge behaviors in a conventional diode-triggered silicon controlled rectifier （DTSCR） is presented in this paper. Combined with the device simulation, a mathematical model is built to get a more in-depth insight into this phenomenon. The theoretical studies are verified by the transmission-line-pulsing （TLP） test results of the modified DTSCR structure, which is realized in a 65-nm complementary metal-oxide-semiconductor （CMOS） process. The detailed analysis of the physical mechanism is used to provide predictions as the DTSCR-based protection scheme is required. In addition, a method is also presented to achieve the tradeoff between the leakage and trigger voltage in DTSCR.

Low-leakage diode-triggered silicon controlled rectifier for electrostatic discharge protection in 0.18-μm CMOS process

A diode-triggered silicon controlled rectifier (DTSCR) is being developed as an electrostatic discharge (ESD) pro- tection device for low voltage applications. However, DTSCR leaks high current during normal operation due to the Darlington effect of the triggering-assist diode string. In this study, two types of diode string triggered SCRs are designed for low leakage consideration; the modified diode string and composite polysilicon diode string triggered SCRs (MDTSCR & PDTSCR). Com- pared with the conventional DTSCR (CDTSCR), the MDTSCR has a much lower substrate leakage current with a relatively large silicon cost, and the PDTSCR has a much lower substrate leakage current with similar area and shows good leakage performance at a high temperature. Other DTSCR ESD properties are also investigated, especially regarding their layout, triggering voltage and failure current.

Electrostatic Discharge Effects on the High-voltage Solar Array

A certain number of charges are deposited on the surface of high-voltage solar array because of effects of space plasma,high-energy charged particles,and solar illumination,hence the surface is charged.Phenomena of electrostatic discharge(ESD) occur on the surface when the deposited charges exceed a threshold amount.In this paper,the mechanism of this ESD is discussed.The ground simulation experiment of the ESD using spacecraft material under surface charging is described,and a novel ESD protecting method for high-voltage solar array,i.e.an active protecting method based on the local strong electric field array is proposed.The results show that the reversal potential gradient field between the cover surface and the substrate materials of high-voltage solar array is a triggering factor for the ESD on the array.The threshold voltage for the ESD occurring on the surface is about 500 V.The charged particles could be deflected using the electric field active protecting method,and hence the ESD on the surface is avoided even when the voltage on the conductor array increases to a certain value.These results pave the way for further developing the protecting measures for high-voltage solar arrays.

Whole-Chip ESD Protection Design for RF and AMS ICs

As integrated circuits （IC） technologies advance into very-deep-sub-micron （VDSM）, electrostatic discharge （ESD） failure becomes one of the most devastating IC reliability problems and on-chip ESD protection design emerges as a major challenge to radio frequency （RF）, analog, and mixed-signal （AMS） IC designs. This paper reviews key design aspects and recent advances in whole-chip ESD protection designs for RF/AMS IC applications in CMOS technologies.

一种新型结构栅耦合ggNMOS ESD保护电路研究

针对现有栅耦合NMOS(gate coupled NMOS,gcNMOS)静电放电(electrostatic discharge,ESD)保护电路对特定ESD脉冲不能及时响应造成的"触发死区"现象,本文提出了一种全新结构的栅耦合栅接地NMOS(gate coupled gate grounded NMOS,gc-ggNMOS)ESD保护电路,这种结构通过利用保护电路中漏、栅交叠区的寄生电容作为耦合电容,连接保护电路栅与地的多晶硅(poly)电阻作为耦合电阻,在有效解决原有gcNMOS结构"触发死区"现象的同时,还避免了因引入特定耦合电容带来版图面积的增加,进而提高了ESD保护电路鲁棒性指标。本文采用ISE-TCAD仿真软件,建立了0.6μm CSMC6S06DPDM-CT02CMOS工艺下gc-ggNMOS ESD保护电路的3D物理结构模型,并对此种结构中关键性参数耦合电阻、电容与触发电压特性的关系进行了系统仿真。仿真表明,当耦合电容为定值时,保护电路触发电压随耦合电阻阻值的增加而减小,这一结果与流片的传输线脉冲(transmission line pulsing,TLP)测试结果吻合。全新结构的gc-ggNMOS ESD保护电路通过了5KV人体放电模式(human body model,HBM)测试。本文的研究结果为次亚微米MOS ESD保护电路的设计提供了一种新的参考依据。

LDMOS-SCR ESD器件漂移区长度对器件性能的影响

采用软件仿真一系列的横向扩散金属氧化物半导体(Laterally diffused metal oxide semiconductor,LDMOS)可控硅(Silicon controlled rectifier,SCR)静电放电(Electrostatic discharge,ESD)保护器件,获取工作状态的I-V曲线。结果表明,随着漂移区间距缩小,单位面积的失效电流增大,器件的ESD保护水平提高,但器件的维持电压减小,器件的鲁棒性降低。仿真提取关键点的少数载流子浓度、电流密度、电压强度等电学特性,根据采样结果和理论分析,内部载流子输运能力增强,但导通电阻无明显变化是该现象的内在原因。采用0.5μm 5V/18V CDMOS(Complementary and double-diffusion MOS,互补型MOS和双扩散型MOS集成)工艺流片并测试器件,测试结果证实了仿真结论。为了提高器件的失效电流且不降低维持电压,利用忆阻器无源变阻的特性,提出了一种新型的LDMOS-SCR ESD保护器件(M-ESD器件),理论分析表明,该器件内部忆阻器与寄生晶体管组成的系统能够有效地协同工作,在不增大芯片面积和不降低维持电压的情况下,使器件的失效电流增加,提高器件保护水平。

A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection

The turn-on speed of electrostatic discharge （ESD） protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device （DTSCR） can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors. Using the variation lateral base doping （VLBD） structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure （VLBD_DTSCR） is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n-p-n and p--n-p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current.

Insight into multiple-triggering effect in DTSCRs for ESD protection

The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.

Novel LDNMOS embedded SCR with strong ESD robustness based on 0.5 μm 18 V CDMOS technology

A novel LDNMOS embedded silicon controlled rectifier(SCR) was proposed to enhance ESD robustness of high-voltage(HV) LDNMOS based on a 0.5 μm 18 V CDMOS process. A two-dimensional(2D) device simulation and a transmission line pulse(TLP) testing were used to analyze the working mechanism and ESD performance of the novel device. Compared with the traditional GG-LDNMOS, the secondary breakdown current(It2) of the proposed device can successfully increase from 1.146 A to 3.169 A with a total width of 50 μm, and ESD current discharge efficiency is improved from 0.459 m A/μm2 to 1.884 m A/μm2. Moreover, due to their different turn-on resistances(Ron), the device with smaller channel length(L) owns a stronger ESD robustness per unit area.

静电注入对55nm MV/HV GGNMOS ESD性能的影响

静电防护问题是提升集成电路可靠性面临的主要挑战之一。基于55 nm HV CMOS工艺,研究了静电注入对中压(MV)和高压(HV)GGNMOS(Gate-Grounded NMOS)器件静电防护性能的影响。研究结果表明,对MV GGNMOS器件来说,静电注入能够在有效降低开启电压(V_(t))、保持电压(V_(h))的同时,减小对二次击穿电流(I_(t2))的影响,且注入面积的改变对器件性能的影响极为有限;对HV GGNMOS器件来说,提高静电注入浓度能够有效提高静电防护能力。

基于130nm SOI工艺数字ASIC ESD防护设计

绝缘体上硅(SOI)工艺具有寄生电容小、速度快和抗闩锁等优点,成为低功耗和高性能集成电路(IC)的首选。但SOI工艺IC更易受自加热效应(SHE)的影响,因此静电放电(ESD)防护设计成为一大技术难点。设计了一款基于130 nm部分耗尽型SOI(PD-SOI)工艺的数字专用IC(ASIC)。针对SOI工艺ESD防护设计难点,进行了全芯片ESD防护原理分析,通过对ESD防护器件、I/O管脚ESD防护电路、电源钳位电路和ESD防护网络的优化设计,有效减小了SHE的影响。该电路通过了4.5 kV人体模型ESD测试,相比国内外同类电路有较大提高,可以为深亚微米SOI工艺IC ESD防护设计提供参考。

A new pin-to-plate corona discharger with clean air protection for particulate matter removal

High concentration particulate matter(PM)has been a serious environmental problem in China and other devel-oping countries.Electrostatic-based purification technology is a method to remove airborne particles,and can reduce the energy consumption of ventilation fans in buildings because of its low pressure drop.In this study,we developed a new pin-to-plate corona discharger with particle-free external air protection to prevent particles polluting the surface of discharge pins.By using an optical microscope,we observed a certain number of parti-cles deposited on the non-protected(exposed pins)and few particles deposited on the protected pins after they operating for 3 weeks.We experimentally studied the long-term performances of the exposed and protected pins in single-pass PM removal efficiency and ozone production.The results showed that the protected pins produce less ozone and have higher breakdown voltage than the exposed pins.Experimental results indicated that the im-proved pin-to-plate corona discharger has better long-term performance and is safer than the exposed one.The results of the research can give an understanding of how to improve electrostatic-based purification technologies toward stable discharging for high removal efficiency of particles.

高压GGNMOS器件结构及工艺对ESD防护特性的影响

基于高压CMOS工艺,对高压栅极接地N型金属氧化物半导体(Highvoltagegrounded-gate N-metal-oxide-semiconductor, HV-GGNMOS)的静电放电(Electrostatic discharge, ESD)防护性能进行研究。由于强折回特性以及失效电流低,HV-GGNMOS在实际应用中受到限制。本文通过计算机辅助设计技术仿真及传输线脉冲实验研究了工艺参数及版图结构对器件ESD防护性能的影响。结果表明,增加漂移区掺杂浓度可以有效提高器件失效电流;加强体接触和增加漂移区长度可以提高器件的维持电压,但失效电流会有所下降,占用版图面积也会更大。

The Biological Property of Synthetic Evolved Digital Circuits with ESD Immunity - Redundancy or Degeneracy？

In the ongoing evolutionary process, biological systems have displayed a fundamental and remarkable property of robustness, i.e., the property allows the system to maintain its functions despite external and internal perturbations. Redundancy and degeneracy are thought to be the underlying structural mechanisms of biological robustness. Inspired by this, we explored the proximate cause of the immunity of the synthetic evolved digital circuits to ESD interference and discussed the biological characteristics behind the evolutionary circuits. First, we proposed an evolutionary method for intrinsic immune circuit design. The circuits＇ immunity was evaluated using the functional fault models based on probability distributions. Then, several benchmark circuits, including ADDER, MAJORITY, and C17, were evolved for high intrinsic immunity. Finally, using the quantitative definitions based on information theory, we measured the topological characteristics of redundancy and degeneracy in the evolved circuits and compared their contributions to the immunity. The results show that redundant elements are neces- sary for the ESD immune circuit design, whereas degeneracy is the key to making use of the redundancy robustly and efficiently.

医用电气设备静电放电(ESD)抗扰度试验分析

本文介绍了静电放电(ESD)的形成机理、放电模型以及耦合方式,创新性地从静电放电(ESD)耦合路径入手,对静电放电(ESD)的干扰机理和抑制对策进行研究。根据电磁兼容(EMC)中静电放电(ESD)的理论研究和试验方法,针对耦合路径设计整改对策,确保整改对策的有效性和可复现性,以此提高静电放电(ESD)整改成功率。