High holding voltage SCR for robust electrostatic discharge protection

A novel silicon controlled rectifier（SCR） with high holding voltage（Vh） for electrostatic discharge（ESD） protection is proposed and investigated in this paper. The proposed SCR obtains high Vhby adding a long N＋ layer（LN＋） and a long P＋ layer（LP＋）, which divide the conventional low voltage trigger silicon controlled rectifier（LVTSCR） into two SCRs（SCR1： P＋/Nwell/Pwell/N＋ and SCR2： P＋/LN＋/LP＋/N＋） with a shared emitter. Under the low ESD current（IESD）, the two SCRs are turned on at the same time to induce the first snapback with high V_h（V_（h1））. As the IESDincreases, the SCR2 will be turned off because of its low current gain. Therefore, the IESDwill flow through the longer SCR1 path, bypassing SCR2, which induces the second snapback with high V_h（V_（h2））. The anti-latch-up ability of the proposed SCR for ESD protection is proved by a dynamic TLP-like（Transmission Line Pulse-like） simulation. An optimized V_（h2） of 7.4 V with a maximum failure current（I_（t2）） of 14.7 m A/μm is obtained by the simulation.

An improved GGNMOS triggered SCR for high holding voltage ESD protection applications

Developing an electrostatic discharge（ESD） protection device with a better latch-up immunity has been a challenging issue for the nanometer complementary metal-oxide semiconductor（CMOS） technology. In this work, an improved grounded-gate N-channel metal-oxide semiconductor（GGNMOS） transistor triggered silicon-controlled rectifier（SCR）structure, named GGSCR, is proposed for high holding voltage ESD protection applications. The GGSCR demonstrates a double snapback behavior as a result of progressive trigger-on of the GGNMOS and SCR. The double snapback makes the holding voltage increase from 3.43 V to 6.25 V as compared with the conventional low-voltage SCR. The TCAD simulations are carried out to verify the modes of operation of the device.

Design of a novel high holding voltage LVTSCR with embedded clamping diode

In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier(LVTSCR), a novel LVTSCR with embedded clamping diode(DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p+implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p+implant region and the n+bridge, which helps to improve the holding voltage and decrease the snapback region.The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse(TLP)tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5–7 V.

Enhanced gated-diode-triggered silicon-controlled rectifier for robust electrostatic discharge (ESD) protection applications

A robust electron device called the enhanced gated-diode-triggered silicon-controlled rectifier (EGDTSCR) for electrostatic discharge (ESD) protection applications has been proposed and implemented in a 0.18-μm 5-V/24-V BCD process. The proposed EGDTSCR is constructed by adding two gated diodes into a conventional ESD device called the modified lateral silicon-controlled rectifier (MLSCR). With the shunting effect of the surface gated diode path, the proposed EGDTSCR, with a width of 50 μm, exhibits a higher failure current (i.e., 3.82 A) as well as a higher holding voltage (i.e., 10.21 V) than the MLSCR.

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor （STSCR- LDMOS） stacked structure is proposed and simulated using the transimission line pulser （TLP） multiple-pulse simulation method in a 0.35μm, 60-V biploar-CMOS-DMOS （BCD） process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metaloxide semiconductor （SCR-LDMOS） in high-voltage electro-static discharge （ESD） protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

高压GGNMOS器件结构及工艺对ESD防护特性的影响

基于高压CMOS工艺,对高压栅极接地N型金属氧化物半导体(Highvoltagegrounded-gate N-metal-oxide-semiconductor, HV-GGNMOS)的静电放电(Electrostatic discharge, ESD)防护性能进行研究。由于强折回特性以及失效电流低,HV-GGNMOS在实际应用中受到限制。本文通过计算机辅助设计技术仿真及传输线脉冲实验研究了工艺参数及版图结构对器件ESD防护性能的影响。结果表明,增加漂移区掺杂浓度可以有效提高器件失效电流;加强体接触和增加漂移区长度可以提高器件的维持电压,但失效电流会有所下降,占用版图面积也会更大。

维持电压和失效电流线性可调节的高压ESD器件

为了研究可控硅结构的静电释放保护器件结构尺寸与性能的关系,采用0.5μm的5 V/18 V CDMOS工艺流片两组SCR ESD器件,使用传输线脉冲测试系统测试器件的性能参数。实验结果表明,随着N阱内P+区和P阱内N+区间距从6μm增加到22μm,ESD器件的维持电压线性增大,从2.29 V升高到9.64 V,幅度达421%;单位面积的失效电流线性减小,幅度约为63%。分析与仿真结果表明,该线性关系具有普遍适用性,可用于调节器件的健壮性和功率耗散能力,满足智能功率集成电路的高压ESD防护需求。另一组随着P阱内P+区和N+区间距增大,维持电压和失效电流呈现非线性的变化,但触发电压迅速降低,可用于实现高压SCR ESD器件的低触发电压设计。

LDMOS-SCR ESD器件漂移区长度对器件性能的影响

采用软件仿真一系列的横向扩散金属氧化物半导体(Laterally diffused metal oxide semiconductor,LDMOS)可控硅(Silicon controlled rectifier,SCR)静电放电(Electrostatic discharge,ESD)保护器件,获取工作状态的I-V曲线。结果表明,随着漂移区间距缩小,单位面积的失效电流增大,器件的ESD保护水平提高,但器件的维持电压减小,器件的鲁棒性降低。仿真提取关键点的少数载流子浓度、电流密度、电压强度等电学特性,根据采样结果和理论分析,内部载流子输运能力增强,但导通电阻无明显变化是该现象的内在原因。采用0.5μm 5V/18V CDMOS(Complementary and double-diffusion MOS,互补型MOS和双扩散型MOS集成)工艺流片并测试器件,测试结果证实了仿真结论。为了提高器件的失效电流且不降低维持电压,利用忆阻器无源变阻的特性,提出了一种新型的LDMOS-SCR ESD保护器件(M-ESD器件),理论分析表明,该器件内部忆阻器与寄生晶体管组成的系统能够有效地协同工作,在不增大芯片面积和不降低维持电压的情况下,使器件的失效电流增加,提高器件保护水平。

内嵌PMOS的高维持电压LVTSCR设计

LVTSCR器件结构相对于普通SCR具有低电压触发特性而被广泛用于集成电路的片上静电放电(ESD)防护中。但是在ESD事件来临时,其维持电压过低易发生闩锁(latch-up)效应致使器件无法正常关断。为改进LVTSCR这一缺陷,提出了一种内嵌PMOS的高维持电压LVTSCR结构,即EmbeddedPMOSLVTSCR(EP-LVTSCR)。该结构基于内嵌PMOS组成的分流通路抽取阱内载流子,抑制寄生晶体管PNP与NPN正反馈效应,来提高器件抗闩锁能力;通过SentaurusTCAD仿真软件模拟0.18μmCMOS工艺,验证器件的电流电压(I-V)特性。实验结果表明,与传统LVTSCR相比较,EP-LVTSCR的维持电压从2.01V提升至4.50V,触发电压从8.54V降低到7.87V。该器件具有良好的电压钳位特性,适用于3.3V电源电路芯片上静电防护应用。

H型栅SOIMOS作为静电保护器件的维持电压的研究(英文)

对绝缘体上硅工艺来说,静电保护可靠性是一个关键且具有挑战性的问题。着重于研究H型栅SOIMOS的维持电压,通过实验发现此器件的维持电压与栅宽紧密联系。结合TCAD仿真解释了器件的工作机理,通过建立集约模型并由HSPICE仿真,揭示了体电阻与维持电压之间的关系。

Holding-voltage drift of a silicon-controlled rectifier with different film thicknesses in silicon-on-insulator technology

This paper presents a new phenomenon,where the holding-voltage of a silicon-controlled rectifier acts as an electrostatic-discharge protection drift in diverse film thicknesses in silicon-on-insulator（SOI） technology. The phenomenon was demonstrated through fabricated chips in 0.18μm SOI technology.The drift of the holding voltage was then simulated,and its mechanism is discussed comprehensively through ISE TCAD simulations.

用于片上ESD防护的新型高维持电压可控硅

为解决闩锁效应,设计了一种新颖的异质结双极晶体管触发可控硅(NHTSCR)。利用异质结晶体管串联反向异质结晶体管来分流SCR的方法,抑制电导调制效应,提高了维持电压。分析了提高NHTSCR维持电压的可行性,详述工作原理,并给出实现步骤。基于Sentaurus TCAD的仿真结果表明,该NHTSCR的维持电压从传统器件的1.34 V提高到3.72 V,在3.3 V工作电压、0.35μm SiGe BiCMOS工艺下,有效避免了闩锁效应。

高温对MOSFET ESD防护器件维持特性的影响

静电放电(electro-static discharge,ESD)防护结构的维持电压是决定器件抗闩锁性能的关键参数,但ESD器件参数的热致变化使得防护器件在高温环境中有闩锁风险.本文研究了ESD防护结构N沟道金属-氧化物-半导体(N-channel metal oxide semiconductor,NMOS)在30—195℃的工作温度下的维持特性.研究基于0.18μm部分耗尽绝缘体上硅工艺下制备的NMOS器件展开.在不同的工作温度下,使用传输线脉冲测试系统测试器件的ESD特性.实验结果表明,随着温度的升高,器件的维持电压降低.通过半导体工艺及器件模拟工具进行二维建模及仿真,提取并分析不同温度下器件的电势、电流密度、静电场、载流子注入浓度等物理参数的分布差异.通过研究以上影响维持电压的关键参数随温度的变化规律,对维持电压温度特性的内在作用机制进行了详细讨论,并提出了改善维持电压温度特性的方法.

基于3D仿真的LDMOS-SCR器件优化

为了提高内嵌可控硅(SCR)的横向扩散金属氧化物半导体(LDMOS-SCR)器件应用于高压时的ESD防护性能,基于0.35μm BCD工艺,在典型LDMOS-SCR(Dut1)基础上,制备了两种实验器件,即阳极环N+区的LDMOS-SCR(Dut2)和在阳极端引入漂移层的LDMOS-SCR(Dut3)。在ESD应力作用下,器件开启后的3DTCAD仿真结果表明,相比于Dut1,Dut2和Dut3的电流密度更小,Dut2和Dut3的导通电阻更大。传输线脉冲的测试结果表明,器件的维持电压分别从2.74V增至8.41V和16.20V,Dut2、Dut3的品质因数较Dut1分别增大了1.96倍、3.52倍。该3DTCAD仿真及版图改进方法可为高压IC的ESD防护设计提供有益参考。

Design of novel DDSCR with embedded PNP structure for ESD protection

A novel dual-directional silicon controlled rectifier（DDSCR） device with embedded PNP structure（DDSCR-PNP） is proposed for electrostatic discharge（ESD） protection, which has greatly reduced latch-up risk owing to the improved holding voltage（V_h/. Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP（PNP_2）. Then, experimental devices are fabricated in a 0.35 m bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the V_h of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width.However, the reduced leakage current（I_L/ of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12 m. Finally, the factors influencing V_h and I_L are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase V_h and decrease I_L. When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased I_L. The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.