一款基于新型Field Programmable Gate Array芯片的投影仪梯形校正系统研究与实现

投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(Field Programmable Gate Array)芯片的新型梯形校正实现方案,解决了校正范围与锯齿失真的矛盾问题,并为进一步成为芯片级产品铺平了道路.图像处理采用kaiser窗函数和sinc函数相结合的方法进行插值,这样的滤波器改善了旁瓣抑制,具有较好的通带性能.介绍了梯形失真的产生和校正原理,提出了利用FPGA芯片XC3S400作为核心图像处理单元的梯形校正系统的硬件和软件实现,说明了该芯片结构、功能及特性,最后提供了校正的效果图.

A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array

A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.

Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA)

An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.

Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software

In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.

Implimentations of SIMD machine using programmable gate array

Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

Implementation of Synchronization Technology in Orthogonal Frequency Division Multiplex System Based on Field Programming Gate Array

In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.

基于FPGA的多路视频采集及AI加速

基于MES50HP开发板及PC主机实现了多源视频采集、拼接及AI协同处理的加速工作。所提出的系统可支持同时采集HDMI、网口、摄像头和光纤4路视频数据,视频采集拼接后,将缩放后存入双倍速率同步动态随机存储器(DDR)中,输出部分分为2路,其中1路数据用于HDMI回环输出,另外1路通过PCIE传至PC主机用于结果显示,并在PC端读取PCIE传回的数据并显示目标检测结果,其中视频采集和目标识别加速部分主要由2块MES50HP开发板构成。本系统在FPGA上实现了卷积加速器,卷积加速器计算完神经网络的一层后再通过PCIE传至主机进行结果显示,卷积计算与图像采集进行深度融合,具有实时、低成本的特点,可广泛应用于边缘计算等领域。实验结果表明:针对红绿灯数据集,该方法在低成本PC主机上实现的最大平均精度均值(mAP)为0.746,最高帧率达45帧。

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

大尺寸机载显示模块动态背光控制系统设计

机载大尺寸液晶显示器(liquid crystal display,LCD)显示模块具有亮度高和功耗大的特点。为了降低其动态功耗,介绍了一种用于大尺寸机载显示模块的动态背光控制系统。该系统采用发光二极管(light emitting diode,LED)动态背光控制技术,通过对背光的动态调节,提高动态显示效果和达到节能的目的。对系统的硬件电路和软件设计算法进行了详细的介绍,并进行实验验证。结果表明,该系统能够有效地提高机载显示模块的动态显示效果,并显著降低了动态功耗。

GJB 5000B在FPGA工程中的应用分析

为引入软件工程化管理办法对设计开发实践实施管理,结合GJB 5000B体系要求,对现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的设计开发流程和GJB 5000B的工程实践要求进行梳理、比对和分析,并提出一套FPGA开发管理在GJB 5000B推进实践中的实施办法。研究成果可为GJB 5000B在FPGA工程中的应用提供一定参考。

FPGA-Based Efficient Programmable Polyphase FIR Filter

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)

面向eFPGA的拼接式布线资源建模方法

嵌入式可编程门阵列核(eFPGA)在定制过程中的每一次迭代,都需要在新生成的布线资源图(RRG)上进行布线,进而完成该次迭代对面积/时序等参数的评估。传统的eFPGA RRG建图方法,在每次评估迭代时都需要重新生成全芯片的结构描述并在其基础上建立布线边和布线点,建图问题复杂度随芯片规模线性增大,很容易达到性能瓶颈。为了应对上述挑战,首先针对复用单元类型建立其RRG模型以及互连关系模型,然后采用一种根据资源排布关系,以动态拼接方式即时生成不同待评估阵列规模RRG的方法。实验证明,其相较于传统方法,在复用单元类型库不变的eFPGA评估过程中,依赖更小且近乎不变的数据库,建图总时间降低了约84%,内存峰值占用平均降低了约64%,从而提高了eFPGA的评估效率。

A novel SRAM test method based on embeddedimplementation on FPGA

With the development of satellite based remote sensors, embedded systems become moreand more popular in space camera electronics. Static Random Access Memory（SRAM） is one kind of themost widely used memories due to its merits of high efficiency and low power dissipation, but testing itsfunction still depends on writing testing modules with hardware description language, which results in lowdeveloping efficiency and low reliability. In this paper, an embedded testing method is proposed, which isbased on MicroBlaze and its speed increasing function design. Implementation of the test method is basedon reusable Intellectual Property（IP） technique and greatly improves data transfer speed. With this method,secondary development of SRAM test system can be made in application layer instead of fundamentallogical layer, which simplifies the system design. It is not only more efficient and more reliable, but alsoeasier to transplant, which greatly reduces test design cost. The validity and feasibility of the method havebeen proved by test results.

Development of a Wireless Capsule Endoscope System Based on Field Programmable Gate Array

A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform, uniform quantization, sub-sampling, differential pulse code modulation (DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array (FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio (PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details. © 2017, Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg.

Implementation of Dynamic Matrix Control on Field Programmable Gate Array

High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.

An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays

We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages,and more parallel units within a stage.It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs),and can be well matched to the placement of the resources on the FPGA.We adopt the decimation-infrequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA.Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz.

高分辨中子闪烁体探测器读出电子学研制

能量分辨中子成像谱仪是中国散裂中子源当前在建的谱仪之一,其衍射探测器90°分区采用6LiF/ZnS中子闪烁体探测器作为探测设备。为实现探测器高位置分辨,读出电子学系统采用了一种电容网络复合读出电路和电荷重心法相结合的实现方法,并研制了电子学样机。该样机由电容网络复合读出电路、前置放大板和数字读出板三部分组成,基本功能验证完成后,分别在实验室和中国散裂中子源的20号束线上进行了相关性能参数测试,测试结果显示:电子学的积分非线性≤0.95%,时间分辨约为12 ns;探测器位置分辨为1 mm、探测效率为65%@1.6?,均达到了工程设计指标。该样机的成功研制为能量分辨中子成像谱仪未来顺利开展谱仪实验提供了可靠的技术保障。

Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH

This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.