A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.

Securing Transmitted Color Images Using Zero Watermarking and Advanced Encryption Standard on Raspberry Pi

Image authentication techniques have recently received a lot of attention for protecting images against unauthorized access.Due to the wide use of the Internet nowadays,the need to ensure data integrity and authentication increases.Many techniques,such as watermarking and encryption,are used for securing images transmitted via the Internet.The majority of watermarking systems are PC-based,but they are not very portable.Hardwarebased watermarking methods need to be developed to accommodate real-time applications and provide portability.This paper presents hybrid data security techniques using a zero watermarking method to provide copyright protection for the transmitted color images using multi-channel orthogonal Legendre Fourier moments of fractional orders(MFrLFMs)and the advanced encryption standard(AES)algorithm on a low-cost Raspberry Pi.In order to increase embedding robustness,the watermark picture is scrambled using the Arnold method.Zero watermarking is implemented on the Raspberry Pi to produce a real-time ownership verification key.Before sending the ownership verification key and the original image to the monitoring station,we can encrypt the transmitted data with AES for additional security and hide any viewable information.The receiver next verifies the received image’s integrity to confirm its authenticity and that it has not been tampered with.We assessed the suggested algorithm’s resistance to many attacks.The suggested algorithm provides a reasonable degree of robustness while still being perceptible.The proposed method provides improved bit error rate(BER)and normalized correlation(NC)values compared to previous zero watermarking approaches.AES performance analysis is performed to demonstrate its effectiveness.Using a 256×256 image size,it takes only 2 s to apply the zero-watermark algorithm on the Raspberry Pi.

A New Method for Impossible Differential Cryptanalysis of 8-Round Advanced Encryption Standard

This paper first presents an impossible differential property for 5-round Advanced Encryption Standard （AES） with high probability. Based on the property and the impossible differential cryptanalytic method for the 5-round AES, a new method is proposed for cryptanalyzing the 8-round AES-192 and AES-256. This attack on the reduced 8-round AES-192 demands 2^121 words of memory, and performs 2^148 8-round AES-192 encryptions. This attack on the reduced 8-round AES-256 demands 2^153 words of memory, and performs 2^180 8-round AES-256 encryptions. Furthermore, both AES-192 and AES-256 require about 2^98 chosen plaintexts for this attack, and have the same probability that is only 2^-3 to fail to recover the secret key.

Impossible differential cryptanalysis of advanced encryption standard

Impossible differential cryptanalysis is a method recovering secret key, which gets rid of the keys that satisfy impossible differential relations. This paper concentrates on the impossible differential cryptanalysis of Advanced Encryption Standard （AES） and presents two methods for impossible differential cryptanalysis of 7-round AES-192 and 8-round AES-256 combined with time-memory trade-off by exploiting weaknesses in their key schedule. This attack on the reduced to 7-round AES-192 requires about 294.5 chosen plaintexts, demands 2129 words of memory, and performs 2157 7-round AES-192 encryptions. Furthermore, this attack on the reduced to 8-round AES-256 requires about 2^101 chosen plaintexts, demands 2^201 words of memory, and performs 2^228 8-round AES-256 encryptions.

Vulnerability Analysis of MEGA Encryption Mechanism

MEGA is an end-to-end encrypted cloud storage platform controlled by users.Moreover,the communication between MEGA client and server is carried out under the protection of Transport Layer Security(TLS)encryption,it is difficult to intercept the key data packets in the process of MEGA registration,login,file data upload,and download.These characteristics of MEGA have brought great difficulties to its forensics.This paper presents a method to attack MEGA to provide an effective method for MEGA’s forensics.By debugging the open-source code of MEGA and analyzing the security white paper published,this paper first clarifies the encryption mechanism of MEGA,including the detailed process of registration,login,and file encryption,studies the encryption mechanism of MEGA from the perspective of protocol analysis,and finds out the vulnerability of MEGA encryption mechanism.On this basis,a method to attack MEGA is proposed,and the secret data stored in the MEGA server can be accessed or downloaded;Finally,the efficiency of the attack method is analyzed,and some suggestions to resist this attack method are put forward.

Dynamically Reconfigurable Encryption System of the AES

Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard （AES） algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.

Split-n-Swap: A New Modification of the Twofish Block Cipher Algorithm

Securing digital data from unauthorized access throughout its entire lifecycle has been always a critical concern.A robust data security system should protect the information assets of any organization against cybercriminal activities.The Twofish algorithm is one of the well-known symmetric key block cipher cryptographic algorithms and has been known for its rapid convergence.But when it comes to security,it is not the preferred cryptographic algorithm to use compared to other algorithms that have shown better security.Many applications and social platforms have adopted other symmetric key block cipher cryptographic algorithms such as the Advanced Encryption Standard(AES)algorithm to construct their main security wall.In this paper,a new modification for the original Twofish algorithm is proposed to strengthen its security and to take advantage of its fast convergence.The new algorithm has been named Split-n-Swap(SnS).Performance analysis of the new modification algorithm has been performed using different measurement metrics.The experimental results show that the complexity of the SnS algorithm exceeds that of the original Twofish algorithm while maintaining reasonable values for encryption and decryption times as well as memory utilization.A detailed analysis is given with the strength and limitation aspects of the proposed algorithm.

Optimizing Region of Interest Selection for Effective Embedding in Video Steganography Based on Genetic Algorithms

With the widespread use of the internet,there is an increasing need to ensure the security and privacy of transmitted data.This has led to an intensified focus on the study of video steganography,which is a technique that hides data within a video cover to avoid detection.The effectiveness of any steganography method depends on its ability to embed data without altering the original video’s quality while maintaining high efficiency.This paper proposes a new method to video steganography,which involves utilizing a Genetic Algorithm(GA)for identifying the Region of Interest(ROI)in the cover video.The ROI is the area in the video that is the most suitable for data embedding.The secret data is encrypted using the Advanced Encryption Standard(AES),which is a widely accepted encryption standard,before being embedded into the cover video,utilizing up to 10%of the cover video.This process ensures the security and confidentiality of the embedded data.The performance metrics for assessing the proposed method are the Peak Signalto-Noise Ratio(PSNR)and the encoding and decoding time.The results show that the proposed method has a high embedding capacity and efficiency,with a PSNR ranging between 64 and 75 dBs,which indicates that the embedded data is almost indistinguishable from the original video.Additionally,the method can encode and decode data quickly,making it efficient for real-time applications.

Energy-efficient and security-optimized AES hardware design for ubiquitous computing

Ubiquitous computing must incorporate a certain level of security. For the severely resource constrained applications, the energy-efficient and small size cryptography algorithm implementation is a critical problem. Hardware implementations of the advanced encryption standard （AES） for authentication and encryption are presented. An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices. It proves that compact AES architectures fail to optimize the AES hardware energy, whereas reducing invalid switching activities and implementing power-optimized sub-modules are the reasonable methods. Implementations of different substitution box （S-Boxes） structures are presented with 0.25μm 1.8 V CMOS （complementary metal oxide semiconductor） standard cell library. The comparisons and trade-offs among area, security, and power are explored. The experimental results show that Galois field composite S-Boxes have smaller size and highest security but consume considerably more power, whereas decoder-switch-encoder S-Boxes have the best power characteristics with disadvantages in terms of size and security. The combination of these two type S-Boxes instead of homogeneous S-Boxes in AES circuit will lead to optimal schemes. The technique of latch-dividing data path is analyzed, and the quantitative simulation results demonstrate that this approach diminishes the glitches effectively at a very low hardware cost.

Data Migration Need, Strategy, Challenges, Methodology, Categories, Risks, Uses with Cloud Computing, and Improvements in Its Using with Cloud Using Suggested Proposed Model (DMig 1)

Data Migration is a multi-step process that begins with analyzing old data and culminates in data uploading and reconciliation in new applications. With the rapid growth of data, organizations constantly need to migrate data. Data migration can be a complex process as testing must be done to ensure data quality. Migration also can be very costly if best practices are not followed and hidden costs are not identified in the early stage. On the other hand, many organizations today instead of buying IT equipment (hardware and/or software) and managing it themselves, they prefer to buy services from IT service providers. The number of service providers is increasing dramatically and the cloud is becoming the preferred tool for more cloud storage services. However, as more information and personal data are transferred to the cloud, to social media sites, DropBox, Baidu WangPan, etc., data security and privacy issues are questioned. So, academia and industry circles strive to find an effective way to secure data migration in the cloud. Various resolving methods and encryption techniques have been implemented. In this work, we will try to cover many important points in data migration as Strategy, Challenges, Need, methodology, Categories, Risks, and Uses with Cloud computing. Finally, we discuss data migration security and privacy challenge and how to solve this problem by making improvements in it’s using with Cloud through suggested proposed model that enhances data security and privacy by gathering Advanced Encryption Standard-256 (ATS256), Data Dispersion Algorithms and Secure Hash Algorithm-512. This model achieves verifiable security ratings and fast execution times.

基于十进制改进的AES算法研究

为使AES算法能在低端设备上应用,且适用于十进制数加密,通过对十进制加密原理和随机加密算法的深入研究,发现在AES中加入随机变量,并适当的修改AES,如:将AES中字节移位改为随机算法用字节交换,随机加密部分用字节交换与四种加密运算,可以有效的提高加解密速度。该文的重点也在于此。经检验,该算法加密强度和AES相当,却适应于十进制数的加密。

Establishment of the Secure Channel between Broker Nodes in Pub/Sub System

The paper mainly discusses the integrity of the forwarded subscription message guaranteed by secure channel which encrypted in data communication by using data encryption standard （DES） algorithm and chaos code algorithm between broker nodes in the routing process of the contentbased publish/subscribe system. It analyzes the security of the secure channel encrypted with data communication by DES algorithm and chaos code algorithm, and finds out the secure channel can be easily attacked by known plain text. Therefore, the paper proposes the improved algorithm of message encryption and authentication, combining encryption and the generation of the message authentication code together to finish scanning at one time, which enhances both the secure degree and running efficiency. This secure channel system has a certain reference value to the pub/sub system requiring highly communication security.

Invariant of Enhanced AES Algorithm Implementations Against Power Analysis Attacks

The security of Internet of Things(IoT)is a challenging task for researchers due to plethora of IoT networks.Side Channel Attacks(SCA)are one of the major concerns.The prime objective of SCA is to acquire the information by observing the power consumption,electromagnetic(EM)field,timing analysis,and acoustics of the device.Later,the attackers perform statistical functions to recover the key.Advanced Encryption Standard(AES)algorithm has proved to be a good security solution for constrained IoT devices.This paper implements a simulation model which is used to modify theAES algorithm using logicalmasking properties.This invariant of the AES algorithm hides the array of bits during substitution byte transformation of AES.This model is used against SCAand particularly Power Analysis Attacks(PAAs).Simulation model is designed on MATLAB simulator.Results will give better solution by hiding power profiles of the IoT devices against PAAs.In future,the lightweight AES algorithm with false key mechanisms and power reduction techniques such as wave dynamic differential logic(WDDL)will be used to safeguard IoT devices against side channel attacks by using Arduino and field programmable gate array(FPGA).

Linear-Differential Cryptanalysis for SPN Cipher Structure and AES

A new attack on block ciphers is introduced, which is termed linear-differential cryptanalysis. It bases the combining of linear cryptanalysis and differential cryptanalysis, and works by using linear-differential probability （LDP）. Moreover, we present a new method for upper bounding the maximum linear-differential probability （MLDP） for 2 rounds of substitution permutation network （SPN） cipher structure. When our result applies to 2-round advanced encryption standard（AES）, It is shown that the upper bound of MLDP is up to 1.68×2^-19, which extends the known results for the 2-round SPN. Furthermore, when using a recursive technique, we obtain that the MLDP for 4 rounds of AES is bounded by 2^-73.

PEM:a lightweight program memory encryption mechanism for embedded processor

Application of embedded systems is faced with multiple threats against security. To solve this problem, this article proposes a new program memory encryption mechanism （PEM） to enhance the security of embedded processor. The new mechanism encrypts all the programs via a secure cache structure. It not only caches the instructions read from the off-chip memory, but also stores the pad values used to encrypt the plaintext. It effectively accelerates encryption and reduces the performance overhead. Besides the encryption, PEM also monitors the program modifications and reset behaviors to reduce the risk of vicious tamper. The experiment indicates that PEM has an average of 2.3 % performance improvement and results in a 25.71% power reduction in the write-back stage. The new scheme offers a good balance between performance and security. It is fully practicable for embedded processor.

A Novel Image Encryption Technique Based on Inter Block Difference

Data security plays a vital role in the current scenario due to the advanced and sophisticated data access techniques. Present development in data access is always a threat to data that are stored in electronic devices. Among all the forms of data, image is an important aspect that still needs methodologies to be stored securely. This work focuses on a novel technique to secure images using inter block difference and advanced encryption standard (AES). The AES algorithm is chosen for encryption since there is no prevalent attack that is successful in analyzing it. Instead of encrypting the entire image, only a part of the image is encrypted. The proposed work is found to reduce the encryption overhead in a significant way and at the same time preserves the safety of the image. It is also observed that the decryption is done in an efficient and time preserving manner.

Arm PSA-Certified IoT Chip Security: A Case Study

With the large scale adoption of Internet of Things(IoT)applications in people’s lives and industrial manufacturing processes,IoT security has become an important problem today.IoT security significantly relies on the security of the underlying hardware chip,which often contains critical information,such as encryption key.To understand existing IoT chip security,this study analyzes the security of an IoT security chip that has obtained an Arm Platform Security Architecture(PSA)Level 2 certification.Our analysis shows that the chip leaks part of the encryption key and presents a considerable security risk.Specifically,we use commodity equipment to collect electromagnetic traces of the chip.Using a statistical T-test,we find that the target chip has physical leakage during the AES encryption process.We further use correlation analysis to locate the detailed encryption interval in the collected electromagnetic trace for the Advanced Encryption Standard(AES)encryption operation.On the basis of the intermediate value correlation analysis,we recover half of the 16-byte AES encryption key.We repeat the process for three different tests;in all the tests,we obtain the same result,and we recover around 8 bytes of the 16-byte AES encryption key.Therefore,experimental results indicate that despite the Arm PSA Level 2 certification,the target security chip still suffers from physical leakage.Upper layer application developers should impose strong security mechanisms in addition to those of the chip itself to ensure IoT application security.

Key Recovery Against 3DES in CPU Smart Card Based on Improved Correlation Power Analysis

The security of CPU smart cards, which are widely used throughout China, is currently being threatened by side-channel analysis. Typical countermeasures to side-channel analysis involve adding noise and filtering the power consumption signal. In this paper, we integrate appropriate preprocessing methods with an improved attack strategy to generate a key recovery solution to the shortcomings of these countermeasures. Our proposed attack strategy improves the attack result by combining information leaked from two adjacent clock cycles. Using our laboratory-based power analysis system, we verified the proposed key recovery solution by performing a successful correlation power analysis on a Triple Data Encryption Standard （3DES） hardware module in a real-life 32-bit CPU smart card. All 112 key bits of the 3DES were recovered with about 80 000 power traces.

A Novel Key Scheduling Scheme for AES Algorithm

This paper examines the theory of AES key scheduling and its potential problems.We propose a novel key scheduling scheme.The scheme improves the speed of key expansion without increasing computational complexity,reduces the dependency of output key on input key during key expansion,and improves the avalanche effect of key expansion.

Formulations of Some Bit Switching Functions in DES

In the data encryption standard （DES） algorithm, there exist several bit-switching functions, including permutations, expansion, and permuted choices. They are generally presented in the form of matrixes and realized by using table look-up technique in the implementation of the cryptosystem. This paper presents explicit formulas for the initial permutation IP, its inverse IP-1 , the expansion function E, and the permuted choice PC_1. It also gives the program realizations of these functions in C＋＋ applying these formulas. With the advantage of the omission of the storage space for these matrixes and the tedious inputs of tables in the implementations of DES, our experimental results shows that the explicit formulas are useful in some situations, such as wireless sensor networks where the memory capacity is limited, especially when the size of file for encrypting is not too large, preferably smaller than 256KB.