Energy-Delay Efficient Unified Routing Protocol for Wireless Sensor Networks

One of the most important challenges in the Wireless Sensor Networks is to improve the performance of the network by extending the lifetime of the sensor nodes. So the focus is on obtaining a trade-off between minimizing the delay involved and reducing the energy consumption of the sensor nodes which directly translate to an extended lifetime of the sensor nodes. An effective Sleep-wake scheduling mechanism can prolong the lifetime of the sensors by eliminating idle power listening, which could result in substantial delays. To counter this, an anycast forwarding scheme that could forward the packet opportunistically to the first awaken node may result in retransmissions as if the chosen node falls in resource constraints. The algorithm, namely Prim’s-Dual is proposed to solve the said problem. The algorithm considers five crucial parameters, namely the residual energy of the nodes, transmission power, receiving power, packet loss rate, interference from which the next hop is determined to extend the lifetime of the sensor node. Since the proposed work is framed keeping critical event monitoring in mind, the sleep-wake scheduling is modified as low-power, high-power scheduling where all nodes are in low-power and the nodes needed for data transmission are respectively turned on to high-power mode. The integrated framework provides several opportunities for performance enhancement for conflict-free transmissions. The aim of our algorithm is to show reliable, energy efficient transfer without compromising on lifetime and delay. The further effectiveness of the protocol is verified. The results demonstrate that the proposed protocol can efficiently handle network scalability with acceptable latency and overhead.

An Elastic Architecture Adaptable to Various Application Scenarios

The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture （EA） to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters （instruction set, branch predictor, data path, memory hierarchy, concurrency, status^zcontrol, and so on） on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP （energy-delay product） for 31.14% in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals＇ lengths and their elasticities.