Applying chemical engineering concepts to non-thermal plasma reactors

Process scale-up remains a considerable challenge for environmental applications of non-thermal plasmas.Undersanding the impact of reactor hydrodynamics in the performance of the process is a key step to overcome this challenge.In this work,we apply chemical engineering concepts to analyse the impact that different non-thermal plasma reactor configurations and regimes,such as laminar or plug flow,may have on the reactor performance.We do this in the particular context of the removal of pollutants by non-thermal plasmas,for which a simplified model is available.We generalise this model to different reactor configurations and,under certain hypotheses,we show that a reactor in the laminar regime may have a behaviour significantly different from one in the plug flow regime,often assumed in the non-thermal plasma literature.On the other hand,we show that a packed-bed reactor behaves very similarly to one in the plug flow regime.Beyond those results,the reader will find in this work a quick introduction to chemical reaction engineering concepts.

Sub-5 nm bilayer GaSe MOSFETs towards ultrahigh on-state current

Dielectric engineering plays a crucial role in the process of device miniaturization.Herein we investigate the electrical properties of bilayer GaSe metal-oxide-semiconductor field-effect transistors(MOSFETs),considering hetero-gate-dielectric construction,dielectric materials and GaSe stacking pattern.The results show that device performance strongly depends on the dielectric constants and locations of insulators.When highk dielectric is placed close to the drain,it behaves with a larger on-state current(I_(on))of 5052μA/μm when the channel is 5 nm.Additionally,when the channel is 5 nm and insulator is HfO2,the largest I_(on) is 5134μA/μm for devices with AC stacking GaSe channel.In particular,when the gate length is 2 nm,it still meets the HP requirements of ITRS 2028 for the device with AA stacking when high-k dielectric is used.Hence,the work provides guidance to regulate the performance of the two-dimensional nanodevices by dielectric engineering.