With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrie...With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.展开更多
研究了基于90 nm e FLASH工艺制备的浮栅型P-Channel FLASH单元的总剂量电离辐射效应,主要研究了FLASH单元随总剂量增加的变化规律及编程/擦除时间对FLASH单元抗总剂量能力的影响。研究表明:随着总剂量的增加,浮栅型P-FLASH器件"开...研究了基于90 nm e FLASH工艺制备的浮栅型P-Channel FLASH单元的总剂量电离辐射效应,主要研究了FLASH单元随总剂量增加的变化规律及编程/擦除时间对FLASH单元抗总剂量能力的影响。研究表明:随着总剂量的增加,浮栅型P-FLASH器件"开"态驱动能力(Idsat)、"关"态漏电(Ioff)及跨导(gm)未发生明显退化,但"擦除/编程"态的阈值窗口明显减小,且呈现"编程"态阈值电压(VTP)下降幅度较"擦除"态(VTE)快的特征;编程/擦除时间的增加会导致FLASH单元阈值电压漂移量,对编程态FLASH单元,编程时间的增大导致阈值电压漂移量增大,而对于擦除态器件FLASH单元,擦除时间的增加导致阈值电压漂移量减小。综上所述,总剂量的增加仅引起浮栅型P-FLASH单元阈值电压的漂移,即浮栅内电荷的转移;编程/擦除时间的增加导致FLASH单元阈值电压漂移量的差异,主要是由于编程/擦除应力时间的增加导致隧道氧化层及界面处陷阱电荷的引入所引起的。展开更多
We evaluate the influence of the thermally assisted tunneling （TAT） mechanism on charge trapping memory （CTM） cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, t...We evaluate the influence of the thermally assisted tunneling （TAT） mechanism on charge trapping memory （CTM） cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, trap depth, distribution of trapped charge, gate voltage and parameters of TAT on erasing/programming speed and retention performance. TAT is an indispensable mechanism in CTM that can increase the detrapping probability of trapped charge. Our results reveal that the TAT effect causes the sensitivity of cell performance to temperature and it could affect the operational speed, especially for the erasing operation. The results show that the retention performance degrades compared with when the TAT mechanism is ignored.展开更多
基金Project supported by the National Basic Research Program of China (Grant Nos. 2010CB934200 and 2011CBA00600)the National Natural Science Foundation of China (Grant Nos. 7360825403, 61176080, and 61176073)the National Science and Technology Major Project of China (Grant No. 2009ZX02023-005)
文摘With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.
文摘研究了基于90 nm e FLASH工艺制备的浮栅型P-Channel FLASH单元的总剂量电离辐射效应,主要研究了FLASH单元随总剂量增加的变化规律及编程/擦除时间对FLASH单元抗总剂量能力的影响。研究表明:随着总剂量的增加,浮栅型P-FLASH器件"开"态驱动能力(Idsat)、"关"态漏电(Ioff)及跨导(gm)未发生明显退化,但"擦除/编程"态的阈值窗口明显减小,且呈现"编程"态阈值电压(VTP)下降幅度较"擦除"态(VTE)快的特征;编程/擦除时间的增加会导致FLASH单元阈值电压漂移量,对编程态FLASH单元,编程时间的增大导致阈值电压漂移量增大,而对于擦除态器件FLASH单元,擦除时间的增加导致阈值电压漂移量减小。综上所述,总剂量的增加仅引起浮栅型P-FLASH单元阈值电压的漂移,即浮栅内电荷的转移;编程/擦除时间的增加导致FLASH单元阈值电压漂移量的差异,主要是由于编程/擦除应力时间的增加导致隧道氧化层及界面处陷阱电荷的引入所引起的。
基金Project supported by the National Basic Research Program of China (Grant No. 2010CB934203)
文摘We evaluate the influence of the thermally assisted tunneling （TAT） mechanism on charge trapping memory （CTM） cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, trap depth, distribution of trapped charge, gate voltage and parameters of TAT on erasing/programming speed and retention performance. TAT is an indispensable mechanism in CTM that can increase the detrapping probability of trapped charge. Our results reveal that the TAT effect causes the sensitivity of cell performance to temperature and it could affect the operational speed, especially for the erasing operation. The results show that the retention performance degrades compared with when the TAT mechanism is ignored.
