Exascale Computer百亿亿次计算机

2020年,中国有望赢得建造世界上首台百亿亿次计算机的竞赛,该计算机每秒运算能力为100亿亿次。至于具体哪台超级计算机将成为第一代超级计算机,目前仍不确定,因为在中国已经有3家机构展开了竞争,分别是位于天津和济南的国家超级计算中心,以及中科曙光(Sugon)。

Challenges and reflections on exascale computing

This paper introduces the development of the exascale （10^18） computing. Though exascalc computing is a hot research direction worldwide, we are facing many challenges in the areas of memory wall, communica- tion wall, reliability wall, power wall and scalability of parallel computing. According to these challenges, some thoughts and strategies are proposed.

A Parallel Hybrid Testing Technique for Tri-Programming Model-Based Software Systems

Recently,researchers have shown increasing interest in combining more than one programming model into systems running on high performance computing systems(HPCs)to achieve exascale by applying parallelism at multiple levels.Combining different programming paradigms,such as Message Passing Interface(MPI),Open Multiple Processing(OpenMP),and Open Accelerators(OpenACC),can increase computation speed and improve performance.During the integration of multiple models,the probability of runtime errors increases,making their detection difficult,especially in the absence of testing techniques that can detect these errors.Numerous studies have been conducted to identify these errors,but no technique exists for detecting errors in three-level programming models.Despite the increasing research that integrates the three programming models,MPI,OpenMP,and OpenACC,a testing technology to detect runtime errors,such as deadlocks and race conditions,which can arise from this integration has not been developed.Therefore,this paper begins with a definition and explanation of runtime errors that result fromintegrating the three programming models that compilers cannot detect.For the first time,this paper presents a classification of operational errors that can result from the integration of the three models.This paper also proposes a parallel hybrid testing technique for detecting runtime errors in systems built in the C++programming language that uses the triple programming models MPI,OpenMP,and OpenACC.This hybrid technology combines static technology and dynamic technology,given that some errors can be detected using static techniques,whereas others can be detected using dynamic technology.The hybrid technique can detect more errors because it combines two distinct technologies.The proposed static technology detects a wide range of error types in less time,whereas a portion of the potential errors that may or may not occur depending on the 4502 CMC,2023,vol.74,no.2 operating environment are left to the dynamic technology,which completes the validation.

西班牙将开发首个ARM架构CPU／GPU混合型超级计算机

西班牙巴塞隆纳超级运算中心（Barcelona Supercomputing Center；BSC）宣布将开发一款混合型超级计算机，其中将首次使用Nvidia公司的Tegra ARM CPU及其支持CUDA的Tesla GPU，期望能够实现达百万兆级（Exascale）的运算性能。

Brief Introduction of TianHe Exascale Prototype System

Facing the challenges of the next generation exascale computing,National University of Defense Technology has developed a prototype system to explore opportunities,solutions,and limits toward the next generation Tianhe system.This paper briefly introduces the prototype system,which is deployed at the National Supercomputer Center in Tianjin and has a theoretical peak performance of 3.15 Pflops.A total of 512 compute nodes are found where each node has three proprietary CPUs called Matrix-2000+.The system memory is 98.3 TB,and the storage is 1.4 PB in total.

Storage wall for exascale supercomputing

The mismatch between compute performance and I/O performance has long been a stumbling block as supercomputers evolve from petaflops to exaflops. Currently, many parallel applications are I/O intensive,and their overall running times are typically limited by I/O performance. To quantify the I/O performance bottleneck and highlight the significance of achieving scalable performance in peta/exascale supercomputing, in this paper, we introduce for the first time a formal definition of the ‘storage wall' from the perspective of parallel application scalability. We quantify the effects of the storage bottleneck by providing a storage-bounded speedup,defining the storage wall quantitatively, presenting existence theorems for the storage wall, and classifying the system architectures depending on I/O performance variation. We analyze and extrapolate the existence of the storage wall by experiments on Tianhe-1A and case studies on Jaguar. These results provide insights on how to alleviate the storage wall bottleneck in system design and achieve hardware/software optimizations in peta/exascale supercomputing.

Application software beyond exascale:challenges and possible trends

With various exascale systems in different countries planned over the next three to five years, developing application software for such unprecedented computing capabilities and parallel scaling becomes a major challenge. In this study, we start our discussion with the current 125-Pflops Sunway TaihuLight system in China and its related application challenges and solutions. Based on our current experience with Sunway TaihuLight, we provide a projection into the next decade and discuss potential challenges and possible trends we would probably observe in future high performance computing software.

Exploring high-performance processor architecture beyond the exascale

The ever-increasing need for high performance in scientific computation and engineering applications will push high-perfornlance computing beyond the exascale. As an integral part of a supercomputing system, high- performance processors and their architecture designs are crucial in improving system performance. In this paper, three architecture design goals for high-performance processors beyond the exa.scale are introduced, including effective performance scaling, efficient resource utilization, and adaptation to diverse applications. Then a high-performance many-core processor architecture with scalar processing and application-specific acceleration （Massa） is proposed, which aims to achieve the above three goals by employing the techniques of distributed computational resources and application-customized hardware. Finally, some future research directions regarding the Massa architecture are discussed.

Force10发布新型交换机ExaScale E系列

Force10网络公司本周发布了一个全新的交换机/路由器产品线,旨在改善虚拟化数据中心和云计算环境的性能、管理和成本效益。

A Pipelining Loop Optimization Method for Dataflow Architecture

With the coming of exascale supercomputing era, power efficiency has become the most important obstacle to build an exascale system. Dataflow architecture has native advantage in achieving high power efficiency for scientific applications. However, the state-of-the-art dataflow architectures fail to exploit high parallelism for loop processing. To address this issue, we propose a pipelining loop optimization method （PLO）, which makes iterations in loops flow in the processing element （PE） array of dataflow accelerator. This method consists of two techniques, architecture-assisted hardware iteration and instruction-assisted software iteration. In hardware iteration execution model, an on-chip loop controller is designed to generate loop indexes, reducing the complexity of computing kernel and laying a good f（mndation for pipelining execution. In software iteration execution model, additional loop instructions are presented to solve the iteration dependency problem. Via these two techniques, the average number of instructions ready to execute per cycle is increased to keep floating-point unit busy. Simulation results show that our proposed method outperforms static and dynamic loop execution model in floating-point efficiency by 2.45x and 1.1x on average, respectively, while the hardware cost of these two techniques is acceptable.