With the increasing demand of computational power in artificial intelligence(AI)algorithms,dedicated accelerators have become a necessity.However,the complexity of hardware architectures,vast design search space,and c...With the increasing demand of computational power in artificial intelligence(AI)algorithms,dedicated accelerators have become a necessity.However,the complexity of hardware architectures,vast design search space,and complex tasks of accelerators have posed significant challenges.Tra-ditional search methods can become prohibitively slow if the search space continues to be expanded.A design space exploration(DSE)method is proposed based on transfer learning,which reduces the time for repeated training and uses multi-task models for different tasks on the same processor.The proposed method accurately predicts the latency and energy consumption associated with neural net-work accelerator design parameters,enabling faster identification of optimal outcomes compared with traditional methods.And compared with other DSE methods by using multilayer perceptron(MLP),the required training time is shorter.Comparative experiments with other methods demonstrate that the proposed method improves the efficiency of DSE without compromising the accuracy of the re-sults.展开更多
Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip （MPSoC）. Tasks of the applications need to be mapped on the MPSoC resources efficiently i...Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip （MPSoC）. Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisity their performance constraints. Exploring all the possible mappings, i.e., tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time, which cannot handle dynamism in applications and resources＇ status. A runtime mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communicationaware design space exploration （CADSE） techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results.展开更多
In performance-based architectural design optimization, the design of building massings and façades is commonly separated, which weakens the effectiveness in performance improvement. In response, this study propo...In performance-based architectural design optimization, the design of building massings and façades is commonly separated, which weakens the effectiveness in performance improvement. In response, this study proposes a hybrid massing-façade integrated design generation and optimization workflow to integrate the two elements in an evolutionary design process. Compared with the existing approaches, the proposed workflow emphasizes the diversity of building design generation, with which various combinations of building massing forms and façade patterns can be systematically explored. Two case studies and a corresponding comparison study are presented to demonstrate the efficacy of the proposed workflow. Results show that the optimization can produce designs coupling the potential of building massings and façades in performance improvement. In addition, the optimization can provide information that supports early-stage architectural design exploration. Such information also enables the architect to understand the performance implications associated with the synergy of building massing and façade design.展开更多
基金the National Key R&D Program of China(No.2018AAA0103300)the National Natural Science Foundation of China(No.61925208,U20A20227,U22A2028)+1 种基金the Chinese Academy of Sciences Project for Young Scientists in Basic Research(No.YSBR-029)the Youth Innovation Promotion Association Chinese Academy of Sciences.
文摘With the increasing demand of computational power in artificial intelligence(AI)algorithms,dedicated accelerators have become a necessity.However,the complexity of hardware architectures,vast design search space,and complex tasks of accelerators have posed significant challenges.Tra-ditional search methods can become prohibitively slow if the search space continues to be expanded.A design space exploration(DSE)method is proposed based on transfer learning,which reduces the time for repeated training and uses multi-task models for different tasks on the same processor.The proposed method accurately predicts the latency and energy consumption associated with neural net-work accelerator design parameters,enabling faster identification of optimal outcomes compared with traditional methods.And compared with other DSE methods by using multilayer perceptron(MLP),the required training time is shorter.Comparative experiments with other methods demonstrate that the proposed method improves the efficiency of DSE without compromising the accuracy of the re-sults.
基金The authors would like to thank the reviewers for their feedback and suggestions. We also wish to mention that this work is partly supported by Singapore Ministry of Education Academic Research Fund Tier 1 （R-263-000-655-133） and National Natural Science Foundation of China （NSFC） （Grant No. 61173032）.
文摘Real-time multi-media applications are increasingly mapped on modern embedded systems based on multiprocessor systems-on-chip （MPSoC）. Tasks of the applications need to be mapped on the MPSoC resources efficiently in order to satisity their performance constraints. Exploring all the possible mappings, i.e., tasks to resources combinations exhaustively may take days or weeks. Additionally, the exploration is performed at design-time, which cannot handle dynamism in applications and resources＇ status. A runtime mapping technique can cater for the dynamism but cannot guarantee for strict timing deadlines due to large computations involved at run-time. Thus, an approach performing feasible compute intensive exploration at design-time and using the explored results at run-time is required. This paper presents a solution in the same direction. Communicationaware design space exploration （CADSE） techniques have been proposed to explore different mapping options to be selected at run-time subject to desired performance and available MPSoC resources. Experiments show that the proposed techniques for exploration are faster over an exhaustive exploration and provides almost the same quality of results.
文摘In performance-based architectural design optimization, the design of building massings and façades is commonly separated, which weakens the effectiveness in performance improvement. In response, this study proposes a hybrid massing-façade integrated design generation and optimization workflow to integrate the two elements in an evolutionary design process. Compared with the existing approaches, the proposed workflow emphasizes the diversity of building design generation, with which various combinations of building massing forms and façade patterns can be systematically explored. Two case studies and a corresponding comparison study are presented to demonstrate the efficacy of the proposed workflow. Results show that the optimization can produce designs coupling the potential of building massings and façades in performance improvement. In addition, the optimization can provide information that supports early-stage architectural design exploration. Such information also enables the architect to understand the performance implications associated with the synergy of building massing and façade design.
