The Advanced Encryption Standard cryptographic algorithm,named AES,is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange.On...The Advanced Encryption Standard cryptographic algorithm,named AES,is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange.One of the most effective physical attacks against the hardware implementation of AES is fault attacks which can extract secret data.Until now,a several AES fault detection schemes against fault injection attacks have been proposed.In this paper,so as to ensure a high level of security against fault injection attacks,a new efficient fault detection scheme based on the AES architecture modification has been proposed.For this reason,the AES 32-bit round is divided into two half rounds and input and pipeline registers are implemented between them.The proposed scheme is independent of the procedure the AES is implemented.Thus,it can be implemented to secure the pipeline and iterative architectures.To evaluate the robustness of the proposed fault detection scheme against fault injection attacks,we conduct a transient and permanent fault attacks and then we determine the fault detection capability;it is about 99.88585%and 99.9069%for transient and permanent faults respectively.We have modeled the AES fault detection scheme using VHDL hardware language and through hardware FPGA implementation.The FPGA results demonstrate that our scheme can efficiently protect the AES hardware implementation against fault attacks.It can be simply implemented with low complexity.In addition,the FPGA implementation performances prove the low area overhead and the high efficiency and working frequency for the proposed AES detection scheme.展开更多
Fault analysis, belonging to indirect attack, is a cryptanalysis technique for the physical implementation of cryptosystem. In this paper, we propose a fault attack on the Balanced Shrinking Generator. The results sho...Fault analysis, belonging to indirect attack, is a cryptanalysis technique for the physical implementation of cryptosystem. In this paper, we propose a fault attack on the Balanced Shrinking Generator. The results show that the attacker can obtain the secret key by analyzing faulty output sequences which is produced by changing control clock of one of Linear Feedback Shift Registers （LFSR）. Therefore, the balanced shrinking generator has a trouble in hardware implementation.展开更多
Since the end of the 1990s,cryptosystems implemented on smart cards have had to deal with two main categories of attacks:side-channel attacks and fault injection attacks.Countermeasures have been developed and validat...Since the end of the 1990s,cryptosystems implemented on smart cards have had to deal with two main categories of attacks:side-channel attacks and fault injection attacks.Countermeasures have been developed and validated against these two types of attacks,taking into account a well-defined attacker model.This work focuses on small vulnerabilities and countermeasures related to the Elliptic Curve Digital Signature Algorithm(ECDSA)algorithm.The work done in this paper focuses on protecting the ECDSA algorithm against fault-injection attacks.More precisely,we are interested in the countermeasures of scalar multiplication in the body of the elliptic curves to protect against attacks concerning only a few bits of secret may be sufficient to recover the private key.ECDSA can be implemented in different ways,in software or via dedicated hardware or a mix of both.Many different architectures are therefore possible to implement an ECDSA-based system.For this reason,this work focuses mainly on the hardware implementation of the digital signature ECDSA.In addition,the proposed ECDSA architecture with and without fault detection for the scalar multiplication have been implemented on Xilinxfield programmable gate arrays(FPGA)platform(Virtex-5).Our implementation results have been compared and discussed.Our area,frequency,area overhead and frequency degradation have been compared and it is shown that the proposed architecture of ECDSA with fault detection for the scalar multiplication allows a trade-off between the hardware overhead and the security of the ECDSA.展开更多
针对同时具有虚假数据注入(false data injection,FDI)攻击与执行器故障下的多无人系统编队协同跟踪问题,提出了一种基于FDI攻击检测机制与故障观测器的韧性容错协同控制新方法。首先,以二阶非线性固定翼无人机模型作为多无人系统研究对...针对同时具有虚假数据注入(false data injection,FDI)攻击与执行器故障下的多无人系统编队协同跟踪问题,提出了一种基于FDI攻击检测机制与故障观测器的韧性容错协同控制新方法。首先,以二阶非线性固定翼无人机模型作为多无人系统研究对象;其次,构建了带有概率约束的贝叶斯概率检测模型对FDI攻击进行检测,作为韧性容错协同控制器的辅助系统;之后,设计了包含执行器故障补偿的韧性容错协同跟踪控制器,并利用Lyapunov稳定性理论证明系统的渐进稳定;最后,通过仿真验证了设计的控制器针对FDI攻击与执行器故障的安全性与可靠性以及编队跟踪能力。展开更多
文摘The Advanced Encryption Standard cryptographic algorithm,named AES,is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange.One of the most effective physical attacks against the hardware implementation of AES is fault attacks which can extract secret data.Until now,a several AES fault detection schemes against fault injection attacks have been proposed.In this paper,so as to ensure a high level of security against fault injection attacks,a new efficient fault detection scheme based on the AES architecture modification has been proposed.For this reason,the AES 32-bit round is divided into two half rounds and input and pipeline registers are implemented between them.The proposed scheme is independent of the procedure the AES is implemented.Thus,it can be implemented to secure the pipeline and iterative architectures.To evaluate the robustness of the proposed fault detection scheme against fault injection attacks,we conduct a transient and permanent fault attacks and then we determine the fault detection capability;it is about 99.88585%and 99.9069%for transient and permanent faults respectively.We have modeled the AES fault detection scheme using VHDL hardware language and through hardware FPGA implementation.The FPGA results demonstrate that our scheme can efficiently protect the AES hardware implementation against fault attacks.It can be simply implemented with low complexity.In addition,the FPGA implementation performances prove the low area overhead and the high efficiency and working frequency for the proposed AES detection scheme.
基金Supported by the Foundation of National Labora-tory for Modern Communications (51436030105DZ0105)
文摘Fault analysis, belonging to indirect attack, is a cryptanalysis technique for the physical implementation of cryptosystem. In this paper, we propose a fault attack on the Balanced Shrinking Generator. The results show that the attacker can obtain the secret key by analyzing faulty output sequences which is produced by changing control clock of one of Linear Feedback Shift Registers （LFSR）. Therefore, the balanced shrinking generator has a trouble in hardware implementation.
基金The funding was provided by the Deanship of Scientific Research at King Khalid University through Research Group Project[grant number RGP.1/157/42].
文摘Since the end of the 1990s,cryptosystems implemented on smart cards have had to deal with two main categories of attacks:side-channel attacks and fault injection attacks.Countermeasures have been developed and validated against these two types of attacks,taking into account a well-defined attacker model.This work focuses on small vulnerabilities and countermeasures related to the Elliptic Curve Digital Signature Algorithm(ECDSA)algorithm.The work done in this paper focuses on protecting the ECDSA algorithm against fault-injection attacks.More precisely,we are interested in the countermeasures of scalar multiplication in the body of the elliptic curves to protect against attacks concerning only a few bits of secret may be sufficient to recover the private key.ECDSA can be implemented in different ways,in software or via dedicated hardware or a mix of both.Many different architectures are therefore possible to implement an ECDSA-based system.For this reason,this work focuses mainly on the hardware implementation of the digital signature ECDSA.In addition,the proposed ECDSA architecture with and without fault detection for the scalar multiplication have been implemented on Xilinxfield programmable gate arrays(FPGA)platform(Virtex-5).Our implementation results have been compared and discussed.Our area,frequency,area overhead and frequency degradation have been compared and it is shown that the proposed architecture of ECDSA with fault detection for the scalar multiplication allows a trade-off between the hardware overhead and the security of the ECDSA.
文摘针对同时具有虚假数据注入(false data injection,FDI)攻击与执行器故障下的多无人系统编队协同跟踪问题,提出了一种基于FDI攻击检测机制与故障观测器的韧性容错协同控制新方法。首先,以二阶非线性固定翼无人机模型作为多无人系统研究对象;其次,构建了带有概率约束的贝叶斯概率检测模型对FDI攻击进行检测,作为韧性容错协同控制器的辅助系统;之后,设计了包含执行器故障补偿的韧性容错协同跟踪控制器,并利用Lyapunov稳定性理论证明系统的渐进稳定;最后,通过仿真验证了设计的控制器针对FDI攻击与执行器故障的安全性与可靠性以及编队跟踪能力。
