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Scenario-based verification in presence of variability using a synchronous approach
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作者 Jean-Vivien MILLO Frederic MALLET +1 位作者 Anthony COADOU S RAMESH 《Frontiers of Computer Science》 SCIE EI CSCD 2013年第5期650-672,共23页
This paper presents a new model of scenarios, dedicated to the specification and verification of system be- haviours in the context of software product lines (SPL). We draw our inspiration from some techniques that ... This paper presents a new model of scenarios, dedicated to the specification and verification of system be- haviours in the context of software product lines (SPL). We draw our inspiration from some techniques that are mostly used in the hardware community, and we show how they could be applied to the verification of software components. We point out the benefits of synchronous languages and mod- els to bridge the gap between both worlds. 展开更多
关键词 ESTEREL UML MARTE SCENARIO verification feature interaction VARIABILITY
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