期刊文献+
共找到10篇文章
< 1 >
每页显示 20 50 100
A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver with 1/4 rate reconfigurable 4-tap FFE and half-rate slicer in a 28-nm CMOS 被引量:1
1
作者 Yukun He Zhao Yuan +5 位作者 Kanan Wang Renjie Tang Yunxiang He Xian Chen Zhengyang Ye Xiaoyan Gui 《Journal of Semiconductors》 EI CAS CSCD 2024年第6期35-46,共12页
A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-fo... A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply. 展开更多
关键词 transceiver(TRx) feed-forward equalizer(ffe) clock and data recovery(CDR) continuous time linear equalizer(CTLE)
下载PDF
面向芯粒间互连的低功耗发射机驱动设计
2
作者 任博琳 肖立权 +5 位作者 齐星云 张庚 王强 罗章 庞征斌 徐佳庆 《计算机工程与科学》 CSCD 北大核心 2024年第4期599-605,共7页
面向UCIe协议提出的芯粒间互连标准,设计与实验了一种面向芯粒(Chiplet)间互连的低功耗发射机驱动。该驱动电路采用了SST电压模驱动器,功耗仅为CML电流模驱动器结构的1/4。此外,该驱动电路基于可调前馈均衡技术,针对不同的信道衰减调整... 面向UCIe协议提出的芯粒间互连标准,设计与实验了一种面向芯粒(Chiplet)间互连的低功耗发射机驱动。该驱动电路采用了SST电压模驱动器,功耗仅为CML电流模驱动器结构的1/4。此外,该驱动电路基于可调前馈均衡技术,针对不同的信道衰减调整均衡强度,采用去加重均衡的方式提高发射信号质量,最终降低码间干扰。本文设计采用CMOS 28 nm工艺设计,前端仿真结果表明,在0.9 V电压供电时,最大均衡强度为-3.7 dB,当32 Gbps的NRZ信号通过21 mm的信道时(16 GHz奈奎斯特频率处衰减为-2.37 dB),选择合适均衡强度后,输出波形眼图眼高为253 mV(71.8%),眼宽为27 ps(87%),仿真功耗仅为4.0 mW。 展开更多
关键词 芯粒 前馈均衡器 SST驱动器 高速接口电路 发射机
下载PDF
面向112 Gbps PAM4串行接收机的低误码协同自适应均衡器
3
作者 赖明澈 吕方旭 +1 位作者 张庚 许超龙 《计算机工程与科学》 CSCD 北大核心 2023年第6期951-960,共10页
高速串行接口是高性能计算机和数据中心芯片之间互连的核心关键IP。随着业界单通道速率由56 Gbps向112 Gbps发展,高速串行接口的误码率急剧增加,严重影响互连性能和系统稳定性。针对112 Gbps PAM4接收机误码率高的难题,首次采取一种协... 高速串行接口是高性能计算机和数据中心芯片之间互连的核心关键IP。随着业界单通道速率由56 Gbps向112 Gbps发展,高速串行接口的误码率急剧增加,严重影响互连性能和系统稳定性。针对112 Gbps PAM4接收机误码率高的难题,首次采取一种协同自适应均衡器构架,提出了面向3种均衡器的自适应协同均衡算法,能在高插入损耗条件下取得较低误码率;提出了基于判决反馈均衡器的盲自适应均衡算法,能缩短链路训练时间,减少硬件开销。采用12 nm CMOS工艺完成了基于协同自适应均衡器的接收机设计。仿真结果表明,针对经过36.5 dB信道的去加重112 Gbps PAM4信号,采取协同自适应均衡器的接收机误码率小于1e^(-12),收敛周期约400 ns,功耗增幅仅约2.3%。 展开更多
关键词 高速串行接口 自适应均衡算法 连续线性均衡器(CTLE) 前向反馈均衡器(ffe) 判决反馈均衡器(DFE)
下载PDF
A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes 被引量:1
4
作者 张明科 胡庆生 《Journal of Semiconductors》 EI CAS CSCD 2013年第12期115-121,共7页
This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate de... This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm^2. 展开更多
关键词 feed-forward equalizer (ffe decision feedback equalizer (DFE) delay line active-inductive peak-ing current mode logic (CML)
原文传递
一种应用在50~64Gb/s的SERDES接收机中的DSP的设计与实现 被引量:2
5
作者 刘敏 郑旭强 +4 位作者 李伟杰 刘朝阳 徐华 张秋月 刘新宇 《微电子学与计算机》 2022年第11期102-109,共8页
介绍了一种基于4脉冲幅度调制(PAM4)SERDES接收机中的专用数字信号处理器(DSP),主要解决高速串行接口中在50~64 Gb/s的超高速传输速率和20~30 dB大幅度信道衰减下的数据恢复问题.该DSP的32路并行结构使系统能够处理50~64 Gb/s的高速数... 介绍了一种基于4脉冲幅度调制(PAM4)SERDES接收机中的专用数字信号处理器(DSP),主要解决高速串行接口中在50~64 Gb/s的超高速传输速率和20~30 dB大幅度信道衰减下的数据恢复问题.该DSP的32路并行结构使系统能够处理50~64 Gb/s的高速数据信号;同时,应用了16-tap的前馈均衡器(FFE),解决了20~30 dB大幅度信道衰减下的数据恢复问题;运用了最小均方算法(LMS)的自适应算法与FFE结合使用,使其能够在不同的信道衰减下都能够自适应的找到最佳的高频补偿并消除传输信道所产生的衰减影响和码间干扰(ISI)问题;同时,为解决传统判决反馈均衡器(DFE)在实现并行结构时带来的反馈环路的时序紧张问题,采用了预判决式结构改良的DFE,其级联在FFE后用来消除剩余的ISI并判决出正确数据信号从而配合FFE均衡恢复出原数据信号.该DSP架构在通过仿真验证后利用28nm CMOS工艺进行了加工制造,通过仿真验证和测试验证发现其能够在50 Gb/s的传输速率和20~30 dB信道衰减下达到良好的均衡效果.最终的DSP芯片面积为2.02 mm^(2),误码率最低到5.21e-9. 展开更多
关键词 SERDES接收机 信道 数字信号处理器(DSP) 前馈均衡器(ffe) 最小均方算法(LMS)
下载PDF
一种用于背板互连的10 Gbit/s接口电路
6
作者 刘登宝 王子谦 《微电子学》 CAS CSCD 北大核心 2018年第1期71-75,共5页
基于SMIC 40nm CMOS工艺,提出了一种用于背板互连的10Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消... 基于SMIC 40nm CMOS工艺,提出了一种用于背板互连的10Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10Gbit/s,传输信道在Nyquist频率(即5GHz)处的衰减为22.4dB。在1.1V电源电压下,判决器Slicer输入端信号眼图的眼高为198mV,眼宽为83ps。FFE的功耗为31mW,接收机前端放大器的功耗为1.8mW,DFE的功耗为5.4mW。 展开更多
关键词 I/O接口电路 前馈均衡器 判决反馈均衡器 码间干扰
下载PDF
基于FPGA的短距离传输信号实时均衡器
7
作者 张天宇 缪旻 +1 位作者 孙剑 钟康平 《北京信息科技大学学报(自然科学版)》 2022年第3期14-19,共6页
实时均衡系统中,训练和更新抽头系数会占用大量的现场可编程门阵列(field-programmable gate array, FPGA)内部资源,限制系统的吞吐量提升。基于最小均方误差算法,使用一种共享抽头系数的并行前馈均衡器(feed-forward equalizer, FFE)结... 实时均衡系统中,训练和更新抽头系数会占用大量的现场可编程门阵列(field-programmable gate array, FPGA)内部资源,限制系统的吞吐量提升。基于最小均方误差算法,使用一种共享抽头系数的并行前馈均衡器(feed-forward equalizer, FFE)结构,通过在单一FFE单元进行训练和更新抽头系数,其他并行FFE单元共享抽头系数的方式优化均衡器的资源占用规模,使均衡器在保证高吞吐量的同时具备自适应信道变化的能力。在基于L-PIC;单片集成硅基光发射机400 Gbit/s CWDM PAM4传输系统中,选用Xilinx XC7VH580T FPGA器件对应采用的并行FFE结构进行仿真分析,通过并行212个FFE单元实现了对2 km传输的53 GBd PAM 4信号(接收机带宽35 GHz)实时均衡。 展开更多
关键词 现场可编程门阵列(FPGA) 前馈均衡器 并行结构 实时均衡
下载PDF
Enhancements of SDR-Based FPGA System for V2X-VLC Communications
8
作者 Lukas Danys Radek Martinek +3 位作者 Rene Jaros Jan Baros Petr Simonik Vaclav Snasel 《Computers, Materials & Continua》 SCIE EI 2021年第9期3629-3652,共24页
This pilot study focuses on a real measurements and enhancements of a software defined radio-based system for vehicle-to everything visible light communication(SDR-V2X-VLC).The presented system is based on a novel ada... This pilot study focuses on a real measurements and enhancements of a software defined radio-based system for vehicle-to everything visible light communication(SDR-V2X-VLC).The presented system is based on a novel adaptive optimization of the feed-forward software defined equalization(FFSDE)methods of the least mean squares(LMS),normalized LMS(NLMS)and QR decomposition-based recursive least squares(QR-RLS)algorithms.Individual parameters of adaptive equalizations are adjusted in real-time to reach the best possible results.Experiments were carried out on a conventional LED Octavia III taillight drafted directly from production line and universal software radio peripherals(USRP)from National Instruments.The transmitting/receiving elements used multistate quadrature amplitude modulation(M-QAM)implemented in LabVIEW programming environment.Experimental results were verified based on bit error ratio(BER),error vector magnitude(EVM)and modulation error ratio(MER).Experimental results of the pilot study unambiguously confirmed the effectiveness of the proposed solution(longer effective communication range,higher immunity to interference,deployment of higher state QAM modulation formats,higher transmission speeds etc.),as the adaptive equalization significantly improved BER,MER and EVM parameters.The best results were achieved using the QR-RLS algorithm.The results measured on deployed QR-RLS algorithm had significantly better Eb/N0(improved by approx.20 dB)and BER values(difference by up to two orders of magnitude). 展开更多
关键词 5G feed-forward software defined equalization multistate quadrature amplitude modulation software defined radio visible light communication
下载PDF
A Study of Electronic Equalization Scheme Enabling Optically Pre-Filtered 1 bit/s/Hz DWDM Transmission
9
作者 Hirofumi Totsuka Takashi Sugihara +3 位作者 Takashi Mizuochi Hiroshi Kubo Hitoyuki Tagami Kuniaki Motoshima 《光学学报》 EI CAS CSCD 北大核心 2003年第S1期558-559,共2页
A numerical simulation shows that by using electronic equalizers 1 bit/s/Hz spectral efficiency can be attained with the same signal quality as a 0.8 bit/s/Hz system. Waveform distortion due to optical band-limiting i... A numerical simulation shows that by using electronic equalizers 1 bit/s/Hz spectral efficiency can be attained with the same signal quality as a 0.8 bit/s/Hz system. Waveform distortion due to optical band-limiting is corrected with nearly 3 dB improvement of the Q-penalty. 展开更多
关键词 of in with for WDM as ffe DFE A Study of Electronic equalization Scheme Enabling Optically Pre-Filtered 1 bit/s/Hz DWDM Transmission
原文传递
Multi-distributed probabilistically shaped PAM-4 system for intra-data-center networks 被引量:3
10
作者 刘梦丽 高明义 柯俊驰 《Chinese Optics Letters》 SCIE EI CAS CSCD 2021年第11期32-37,共6页
Probabilistically shaped(PS) pulse amplitude modulation(PAM) is a promising technique for intra-data-center networks due to its superior performance, for which a low-complexity and cost-effective distributed matching ... Probabilistically shaped(PS) pulse amplitude modulation(PAM) is a promising technique for intra-data-center networks due to its superior performance, for which a low-complexity and cost-effective distributed matching method is critical. In this work, we propose an energy-level-assigned method to yield PS-PAM-4 signals with various bit rates based on variable probabilistic distributions. We experimentally demonstrate the proposed method in a 25 Gbaud PS-PAM-4 transmission over a bandwidth of approximately 10 GHz. Compared to a uniform PAM-4 system, the proposed multi-distributed PS-PAM-4 system approaches the hard decision threshold at a wide range of received optical power for different applications. 展开更多
关键词 probabilistic shaping pulse amplitude modulation feed-forward equalizer
原文传递
上一页 1 下一页 到第
使用帮助 返回顶部