A 600W Broadband Doherty Power Amplifier with Improved Linearity for Wireless Communication System

An asymmetric Doherty architecture based on three identical transistors is proposed in this paper. This proposed three.way topology reduces the difficulty in designing matching networks brought by the low optimal impedance of high power transistors. And the inverted Doherty topology as well as carefully chosen value of load impedance makes it possible to extend the bandwidth of high power amplifiers. Besides, bias networks of this proposed three.way architecture are also carefully considered to improve the linearity. The proposed high power three.way Doherty power amplifier(3W.DPA) is designed and fabricated based on theoretic analysis. Its maximum output power is about 600 Watts and the drain efficiency is above 35.5% at 9d B back off output power level from 1.9GHz to 2.2 GHz and the saturated drain efficiency is above 47% across the whole frequency band. The measured concurrent two.tone results suggest that the linearity of DPA is improved by at least 5d B.

FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave.It adopts a three-stage single-ended structure at 28GHz.An analog predistortion lmearization method is used to improve the linearity of the power amplifier(PA).As a result,there is a significant improvement in power-added efficiency(PAE)and linearity is achieved.The Ka-band PA is implemented in TSMC 65nm CMOS process.At 1.2V supply voltage,the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%.After linearization,the output power at the ldB compression point is increased by 2dBm,with efficient gain compensation performance.

High linearity U-band power amplifier design:a novel intermodulation point analysis method

A power amplifier’s linearity determines the emission signal’s quality and the efficiency of the system.Nonlinear distortion can result in system bit error,out-of-band radiation,and interference with other channels,which severely influence communication system’s quality and reliability.Starting from the third-order intermodulation point of the milimeter wave(mm-Wave)power amplifiers,the circuit’s nonlinearity is compensated for.The analysis,design,and implementation of linear class AB mm-Wave power amplifiers based on GlobalFoundries 45 nm CMOS silicon-on-insulator(SOI)technology are presented.Three single-ended and differential stacked power amplifiers have been implemented based on cascode cells and triple cascode cells operating in U-band frequencies.According to nonlinear analysis and on-wafer measurements,designs based on triple cascode cells outperform those based on cascode cells.Using single-ended measurements,the differential power amplifier achieves a measured peak power-added efficiency(PAE)of 47.2%and a saturated output power(P_(sat))of 25.2 dBm at 44 GHz.The amplifier achieves a P_(sat)higher than 23 dBm and a maximum PAE higher than 25%in the measured bandwidth from 44 GHz to 50 GHz.

Adaptation of a Digitally Predistorted RF Amplifier Using Selective Sampling

In this paper, a reduced-cost method of measuring residual nonlinearities in an adaptive digitally predistorted amplifier is proposed. Measurements obtained by selective sampling of the amplifier output are integrated over the input envelope range to adapt a fourth-order polynomial predistorter with memory correction. Results for a WCDMA input with a 101 carrier configuration show that a transmitter using the proposed method can meet the adjacent channel leakage ratio （ACLR） specification. Inverse modeling of the nonlinearity is proposed as a future extension that will reduce the cost of the system further.

Design and Analysis of a Power Efficient Linearly Tunable Cross-Coupled Transconductor Having Separate Bias Control

A common current source, generally used to bias cross-coupled differential amplifiers in a transconductor, controls third harmonic distortion (HD3) poorly. Separate current sources are shown to provide better control on HD3) . In this paper, a detailed design and analysis is presented for a transconductor made using this biasing technique. The transconductor, in addition, is made to offer high Gm, low power dissipation and is designed for linearly tunable Gm with current mode load as one of the applications. The circuit exhibits HD3) of less than –43.7 dB, high current efficiency of 1.18 V-1 and Gm of 390 μS at 1 VGp-p @ 50 MHz. UMC 0.18 μm CMOS process technology is used for simulation at supply voltage of 1.8 V.

预畸变对固态雷达脉冲压缩的改善

固态功率放大器是相参雷达的微波源,直接决定雷达的探测性能。功率放大器本身存在的非线性特性引起发射信号畸变,导致脉冲压缩性能降低。使用简化沃特拉(Voltera)模型对雷达发射波形激励下的功放进行建模,采用数字预畸变技术提高发射信号质量。在SaXPol全固态X波段天气雷达上对预畸变算法进行测试,结果表明,发射信号在预畸变前后误差矢量幅度改善约15%,脉冲压缩后峰值旁瓣电平比下降10 dB左右。

Energy-efficient power amplifiers and linearization techniques for massive MIMO transmitters: a review

Highly efficient power amplifiers(PAs)and associated linearization techniques have been developed to accommodate the explosive growth in the data transmission rate and application of massive multiple input multiple output(mMIMO)systems.In this paper,energy-efficient integrated Doherty PA monolithic microwave integrated circuits(MMICs)and linearization techniques are reviewed for both the sub-6 GHz and millimeter-wave(mm-Wave)fifth-generation(5G)mMIMO systems;different semiconductor processes and architectures are compared and analyzed.Since the 5G protocols have not yet been finalized and PA specifications for mMIMO are still under consideration,it is worth investigating novel design methods to further improve their efficiency and linearity performance.Digital predistortion techniques need to evolve to be adapted in mMIMO systems,and some creative linearity enhancement techniques are needed to simultaneously improve the compensation accuracy and reduce the power consumption.

A highly linear fully integrated CMOS power amplifier with an analog predistortion technique

A transformer-based CMOS power amplifier （PA） is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter. The third harmonic of the power stage and driver stage can be cancelled out in a specific power region. The two-stage PA fabricated in a standard 0.18-#m CMOS process delivers 27.5 dBm with 27% PAE at the 1-dB compression point （PldB） and offers 21 dB gain. The PA achieves 5.5 % EVM and meets the spectrum mask at 20.5 dBm average power. Another conventional PA with a zero-cross-point of gm3 bias is also fabricated and compared to prove its good linearity and efficiency.

A high-linearity InGaP/GaAs HBT power amplifier for IEEE 802.11a/n

A three-stage 4.8-6 GHz monolithic power amplifier（PA） compatible with IEEE 802.11a/n designed based on an advanced 2μm InGaP/GaAs hetero-junction bipolar transistor（HBT） process is presented.The PA integrates input matching and closed-loop power control circuits on chip.Under 3.3 V DC bias,the amplifier achieves a ~31 dB small signal gain,excellent wide band input and output matching among overall 1.2 GHz bandwidth,and up to 24.5 dBm linear output power below EVM 3%with IEEE 802.11a 64QAM OFDM input signal.

On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

Three linear CMOS power amplifiers （PAs） with high output power （more than watt-level output power） for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer （PCT） and one 1.95 GHz PA using an on-chip series combining transformer （SCT） to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors （MGTR） and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE.

High linearity 5.2-GHz power amplifier MMIC using CPW structure technology with a linearizer circuit

A built-in linearizer was applied to improve the linearity in a 5.2-GHz power amplifier microwave monolithic integrated circuit（MMIC）,which was undertaken with 0.15-μm AlGaAs/InGaAs D-mode PHEMT technology. The power amplifier（PA） was studied taking into account the linearizer circuit and the coplanar waveguide（CPW） structures.Based on these technologies,the power amplifier,which has a chip size of 1.44×1.10 mm^2,obtained an output power of 13.3 dBm and a power gain of 14 dB in the saturation region.An input third-order intercept point （IIP3） of-3 dBm,an output third-order intercept point（OIP3） of 21.1 dBm and a power added efficiency（PAE） of 22% were attained,respectively.Finally,the overall power characterization exhibited high gain and high linearity,which illustrates that the power amplifier has a compact circuit size and exhibits favorable RF characteristics.This power circuit demonstrated high RF characterization and could be used for microwave power circuit applications at 5.2 GHz.

A New Two-Branch Amplification Architecture and its Application with Various Modulated Signals

This paper proposes a new two-branch amplification architecture that combines baseband signal decomposition with RF front-end optimization. In the proposed architecture, the filtered modulated signals are separated into two components that are then amplified independently and combined to regenerate an amplified version of the original signal. A branch with an efficient amplifier transmits a low-varying envelope signal that contains the main part of the information. Another branch amplifies the residual portion of the signal. The baseband decomposition and parameters of the RF part are optimized to find the configuration that gives the best power efficiency and linearity. For M-ary quadrature amplitude modulation （M-QAM） signals, this technique is limited in terms of power efficiency. However, for filtered continuous phase modulation （CPM） signals, especially for minimum shift keying （MSK） and Gaussian MSK （GMSK） signals, high power efficiency can be achieved with no significant impact on the overall linearity. The results show that this technique gives better performance than the single-ended ctass-B amplifier.

高输出功率高线性度5G毫米波功率放大器研究与设计

本文针对5G毫米波功率放大器(Power amplifier, PA)高输出功率和高线性度的需求,对PA功率和线性度受限机理进行了深入分析。在此基础上,提出了一种采用峰化电感技术和两路合成结构提升输出功率,以及采用PMOS补偿电容、二阶谐波和低阻抗网络来改善宽带调制下线性度的PA电路。基于5G毫米波26GHz频段应用,该PA采用65nm CMOS SOI工艺进行实现。测试结果表明,该PA在26GHz,实现了20.8dBm的OP1dB和21.3dBm的Psat,峰值PAE为26.15%。在调制信号测试中,使用5G NR 400 MHz 1-CC 64-QAM和256-QAM OFDM信号,该PA支持5%和3%的均方根误差矢量幅度(EVM),和实现平均输出功率(Pavg)分别为15.5dBm和14.4dBm。

一种新型模拟预失真线性化器

为解决氮化镓(GaN)固态功率放大器(Solid-State Power Amplifier, SSPA)线性度较差的问题,采用模拟预失真技术设计了一款新型结构的线性化器,将2支肖特基二极管及其管座电路并联,并通过2路偏置电路分别控制,使用微带隔离器减少二极管间的相互干扰,并对输入输出驻波进行改善。通过电路设计软件ADS进行仿真,仿真结果显示,可以实现幅度补偿2.2~6.1 dB,相位补偿21.5°~49°。根据测试数据建立功率放大器非线性模型,与线性化器进行级联仿真。结果表明,目标GaN SSPA饱和输出功率回退3 dB时,可改善三阶互调10 dB以上。进行实物加工及测试,验证了该线性化器可大幅改善功率放大器的线性度。

一种基于双通道非线性反馈架构的模拟域功率放大器线性化技术

该文提出一种在模拟域抑制功率放大器(PA)非线性失真的双通道非线性反馈架构,以改善PA线性度,减少邻道泄露。在该架构中,用于抑制非线性的电路包含非线性提取环路和反馈调整环路。非线性提取环路通过耦合器提取PA输入和输出信号,进行幅度和相位对齐后抵消线性信号,保留PA产生的非线性失真。反馈调整环路包含两条独立反馈通道,且信号通过非线性提取环路和反馈调整环路中两条通道分别反馈后的总时延具有两倍关系,使反馈环路呈现2阶Delta-Sigma结构形式,相比于单通道非线性反馈架构具有更好的失真抑制性能。并且通过所提方法配置反馈通道参数,可以实现不同目标频点下非线性失真的灵活抑制。最后设计了一个使用CMPA0060002F商用功放芯片的实验平台,对于带宽为40 MHz,载频为780 MHz的测试信号,在当前6 ns的硬件反馈时延条件下,可以使邻道功率泄露比(ACLR)单边带改善11 dB或双边带改善6 dB,且通过减小反馈时延能够取得更好的性能。

基于谐波控制的高效线性功率放大器设计

为了满足当前第五代移动通信系统对高速率传输的要求,采用谐波控制的方法设计了一款高效线性功率放大器。结合三阶交调分量的产生机制,综合考虑基带阻抗、基波阻抗及二次谐波阻抗对输出功率、效率和线性度的影响,在保证效率的基础之上,改善功放线性度。并采用紧凑、便于集成的耦合线SIR(Step Impedance Resonator)带通滤波器作为输出匹配网络,实现对谐波的抑制。该功率放大器采用GaN HEMT器件CGH40010F,通过仿真与实物测试,验证了该方案的可行性,最终测试结果表明,功率放大器在中心频率3.4 GHz处,间隔5 MHz的双音信号下,输出功率为37 dBm时,对应的功率附加效率(PAE)为40%,三阶交调失真(IMD3)为-30 dBc,增益约为10.5 dB。

Q波段高线性高效率GaN功率放大器MMIC

针对卫星通信和5G毫米波通信应用,基于深亚微米GaN工艺,开发了一款高功率、高线性和高效率的功率放大器单片微波集成电路(MMIC)。根据器件的最大增益和负载牵引特性确定末级晶体管的总栅宽;根据增益要求采用4级放大器级联,前级、次前级、末前级和末级的栅宽比为1∶2∶4∶8;通过对末级和前三级栅极偏置电压分别加电,实现对各级电路增益分别调节,以提高放大器的线性度;输出匹配网络中包含了二次谐波调谐电路,以降低谐波分量,提高放大器的效率,并结合片外模拟预失真电路实现线性度提升。功率放大器MMIC芯片尺寸为2.6 mm×2.1 mm。测试结果表明,在37~42 GHz,放大器的饱和输出功率大于40 dBm,功率附加效率大于30%,功率增益大于18 dB,三阶交调失真(IMD3)@36 dBm小于-30 dBc。

225MHz~2.5GHz宽带高功率放大器的线性度优化与实现

针对复杂调制信号在通过非线性功率放大器时,会产生严重的带内失真和邻道干扰,造成系统功率效率和频谱效率迅速下降的情况,文中从理论和工程实践方面,分析功率放大器非线性失真特性、产生因素和减弱措施,主要从偏置网络、输入输出匹配网络等方面入手减弱记忆效应,提升视频带宽(VBW)。同时,对电路进行调试优化,设计完成225 MHz~2.5 GHz频段功率放大器输出功率为80 W。使用20 MHz宽带QPSK调制信号进行测试,得出:指标(ACPR)小于-33 dBc,EVM小于2.4%,η在29.7%~39.8%之间,满足设计需求。

毫米波氮化镓包络跟踪功率放大器实验研究

为了提高毫米波功率放大器的回退效率并拓展工作带宽,文中对毫米波频段氮化镓包络跟踪(Envelope Tracking,ET)功率放大器进行了实验研究。采用0.15μm氮化镓工艺的功放芯片,由线性电源调制器馈电,进一步采用数字预失真技术改善输出波形的非线性失真来提高线性电源调制器的工作带宽,最终在提高功放芯片效率的同时提升了其线性度。实验测试结果表明,在23~28 GHz频率范围内,当分别采用40MHz带宽峰均比为8.6 dB和80 MHz带宽峰均比为6.4 dB的正交频分复用(OFDM)64QAM调制信号进行测试时,恒压供电的功率放大器的回退效率分别为7.5%~10.1%和12.3%~16.5%,而采用线性电源调制器供电的ET功放回退效率为9.6%~14.3%和16.3%~22.1%,平均提升3%~6%左右,经过数字预失真处理后的邻近信道功率泄漏比均低于-30.1 dBc。