Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack

We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors(FeFETs)with metal/ferroelectric/interlayer/Si(MFIS)gate stack structure.In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect,we first establish a model to simulate the electron trapping behavior in n-type Si FeFET.The model is based on the quantum mechanical electron tunneling theory.And then,we use the pulsed I_d-V_g method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET.Our model fits the experimental data well.By fitting the model with the experimental data,we get the following conclusions.(i)During the positive operation pulse,electrons in the Si substrate are mainly trapped at the interface between the ferroelectric(FE)layer and interlayer(IL)of the FeFET gate stack by inelastic trap-assisted tunneling.(ii)Based on our model,we can get the number of electrons trapped into the gate stack during the positive operation pulse.(iii)The model can be used to evaluate trap parameters,which will help us to further understand the fatigue mechanism of FeFET.

Determining the influence of ferroelectric polarization on electrical characteristics in organic ferroelectric field-effect transistors

Organic ferroelectric field-effect transistors （OFeFETs） are regarded as a promising technology for low-cost flexible memories. However, the electrical instability is still a critical obstacle, which limits the commercialization process. Based on already established models for polarization in ferroelectrics and charge transport in OFeFETs, simulation work is performed to determine the influence of polarization fatigue and ferroelectric switching transient on electrical characteristics in OFeFETs. The polarization fatigue results in the decrease of the on-state drain current and the memory window width and thus degrades the memory performance. The output measurements during the ferroelectric switching process show a hysteresis due to the instable polarization. In the on/off measurements, a large writing/erasing pulse frequency weakens the polarization modulation and thus results in a small separation between on- and off-state drain currents. According to the electrical properties of the ferroelectric layer, suggestions are given to obtain optimal electrical characterization for OFeFETs.

A Back-Gated Ferroelectric Field-Effect Transistor with an Al-Doped Zinc Oxide Channel

We report a back-gated metal-oxide-ferroelectric-metal （MOFM） field-effect transistor （FET） with lead zirconate titanate （PZT） material, in which an Al doped zinc oxide （AZO） channel layer with an optimized doping concentration of 1% is applied to reduce the channel resistance of the channel layer, thus guaranteeing a large enough load capacity of the transistor. The hysteresis loops of the Pt/PZT/AZO/Ti/Pt capacitor are measured and compared with a Pt/PZT/Pt capacitor, indicating that the remnant polarization is almost 40 μC/cm^2 and the polarization is saturated at 20 V. The measured capacitance-voltage properties are analyzed as a result of the electron depletion and accumulation switching operation conducted by the modulation of PZT on AZO channel resistance caused by the switchable remnant polarization of PZT. The switching properties of the AZO channel layer are also proved by the current-voltage transfer curves measured in the back-gated MOFM ferroelectric FET, which also show a drain current switching ratio up to about 100 times.

Field-effect transistor memories based on ferroelectric polymers

Field-effect transistors based on ferroelectrics have attracted intensive interests, because of their non-volatile data retention, rewritability, and non-destructive read-out. In particular, polymeric materials that possess ferroelectric properties are promising for the fabrications of memory devices with high performance, low cost, and large-area manufacturing, by virtue of their good solubility, low-temperature processability, and good chemical stability. In this review, we discuss the material characteristics of ferroelectric polymers, providing an update on the current development of ferroelectric field-effect transistors（Fe-FETs） in non-volatile memory applications.

Low-Programmable-Voltage Nonvolatile Memory Devices Based on Omega-shaped Gate Organic Ferroelectric P(VDF-TrFE) Field Effect Transistors Using p-type Silicon Nanowire Channels

A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene)(P(VDF-Tr FE)). We overcame the interfacial layer problem by incorporating P(VDF-Tr FE) as a ferroelectric gate using a low-temperature fabrication process. Our memory devices exhibited excellent memory characteristics with a low programming voltage of ±5 V, a large modulation in channel conductance between ON and OFF states exceeding 105, a long retention time greater than 3 9 104 s, and a high endurance of over 105 programming cycles while maintaining an ION/IOFFratio higher than 102.

Overview of one transistor type of hybrid organic ferroelectric non-volatile memory

Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent years.This emerging type of memory devices can lead to a new instrument system as a potential alternative to previous non-volatile memory building blocks in future processing units because of their numerous merits such as cost-effective process,simple structure and freedom in substrate choices.This bi-stable non-volatile memory device of information storage has been investigated using several organic or inorganic semiconductors with organic ferroelectric polymer materials.Recent progresses in this ferroelectric memory field,hybrid system have attracted a lot of attention due to their excellent device performance in comparison with that of all organic systems.In this paper,a general review of this type of ferroelectric non-volatile memory is provided,which include the device structure,organic ferroelectric materials,electrical characteristics and working principles.We also present some snapshots of our previous study on hybrid ferroelectric memories including our recent work based on zinc oxide nanowire channels.

Sensing with extended gate negative capacitance ferroelectric field-effect transistors

With major signal analytical elements situated away from the measurement environment,extended gate(EG)ion-sensitive fieldeffect transistors(ISFETs)offer prospects for whole chip circuit design and system integration of chemical sensors.In this work,a highly sensitive and power-efficient ISFET was proposed based on a metal-ferroelectric-insulator gate stack with negative capacitance–induced super-steep subthreshold swing and ferroelectric memory function.Along with a remotely connected EG electrode,the architecture facilitates diverse sensing functions for future establishment of smart biochemical sensor platforms.

Observing suppressed polarization in flexible ferroelectric negative capacitance field effect transistors

Negative capacitance(NC)has the potential to enable low power microelectronics beyond the fundamental thermionic limit,and it has been theorized that the thermodynamically unstable NC of ferroelectrics can be stabilized by linear dielectric,making negative capacitance ferroelectric field effect transistors(NC-FeFET)possible.Nevertheless,the validity of NC as a physical concept for ferroelectrics remain contentious despite numerous theoretical and experimental investigations,and the intrinsic ferroelectric NC with suppressed polarization has not been demonstrated except locally at vortex core.While NC-FeFET with subthreshold swing(SS)lower than 60 mV/dec limit has been reported,such device characteristics has not been directly connected to suppressed polarization at materials’level,and alternative mechanisms other than NC have also been proposed.Here we demonstrate stable sub-60 mV/dec SS with hysteresis free Isingle bondV in NC-FeFET based on SrTiO_(3)/Pb(Zr_(0.1)Ti_(0.9))O_(3)/SrTiO_(3) heterostructure,and observe its suppressed polarization at both macroscopic and microscopic scales.The intrinsic ferroelectric NC thus is experimentally confirmed and directly connected to NC-FeFET performance,and the mica-based device is also highly flexible and robust under cyclic bending as well as extended heating.

Giant piezotronic effect in ferroelectric field effect transistor

The piezotronics effect utilizes a piezopotential to modulate and control current in piezo-semiconductors.Ferroelectric materials,as a type of piezoelectric materials,possess piezoelectric coefficients that are significantly larger than those found in conventional piezoelectric materials.Here,we propose a strain modulated ferroelectric field-effect transistor(St-FeFET)utilizing external strain instead of gate voltage to achieve ferroelectric modulation,which eliminates the need for gate voltage.By applying a very small strain(0.01%),the St-FeFET can achieve a maximum on-off current ratio of 1250%and realizes a gauge factor(GF)of 1.19×10^(6),which is much higher than that of conventional strain sensors.This work proposes a new method for realizing highly sensitive strain sensors and presents innovative approaches to the operation methods of ferroelectric field-effect transistors as well as potential applications for coupling of strain sensors and various devices across different fields.

Dual-logic-in-memory implementation with orthogonal polarization of van der Waals ferroelectric heterostructure

The rapid advancement of AI-enabled applications has resulted in an increasing need for energy-efficient computing hardware.Logic-in-memory is a promising approach for processing the data stored in memory,wherein fast and efficient computations are possible owing to the parallel execution of reconfigurable logic operations.In this study,a dual-logic-in-memory device,which can simultaneously perform two logic operations in four states,is demonstrated using van der Waals ferroelectric field-effect transistors(vdW FeFETs).The proposed dual-logic-in-memory device,which also acts as a twobit storage device,is a single bidirectional polarization-integrated ferroelectric field-effect transistor(BPI-FeFET).It is fabricated by integrating an in-plane vdW ferroelectric semiconductor SnS and an out-of-plane vdW ferroelectric gate dielectric material—CuInP_(2)S_(6).Four reliable resistance states with excellent endurance and retention characteristics were achieved.The two-bit storage mechanism in a BPI-FeFET was analyzed from two perspectives:carrier density and carrier injection controls,which originated from the out-of-plane polarization of the gate dielectric and in-plane polarization of the semiconductor,respectively.Unlike conventional multilevel FeFETs,the proposed BPIFeFET does not require additional pre-examination or erasing steps to switch from/to an intermediate polarization,enabling direct switching between the four memory states.To utilize the fabricated BPI-FeFET as a dual-logic-inmemory device,two logical operations were selected(XOR and AND),and their parallel execution was demonstrated.Different types of logic operations could be implemented by selecting different initial states,demonstrating various types of functions required for numerous neural network operations.The flexibility and efficiency of the proposed dual-logic-in-memory device appear promising in the realization of next-generation low-power computing systems.

Challenges and recent advances in HfO_(2)-based ferroelectric films for non-volatile memory applications

The emergence of data-centric applications such as artificial intelligence(AI),machine learning,and the Internet of Things(IoT),has promoted surges in demand for storage memories with high operating speed and nonvolatile characteristics.HfO_(2)-based ferroelectric memory technologies,which emerge as a promising alternative,have attracted considerable attention due to their high performance,energy efficiency,and full compatibility with the standard complementary metal-oxide-semiconductors(CMOS)process.These nonvolatile storage elements,such as ferroelectric random access memory(FeRAM),ferroelectric field-effect transistors(FeFETs),and ferroelectric tunnel junctions(FTJs),possess different data access mechanisms,individual merits,and specific application boundaries in next-generation memories or even beyond von Neumann architecture.This paper provides an overview of ferroelectric HfO2 memory technologies,addresses the current challenges,and offers insights into future research directions and prospects.

Subthermionic field-effect transistors with sub-5 nm gate lengths based on van der Waals ferroelectric heterostructures

Overcoming the sub-5 nm gate length limit and decreasing the power dissipation are two main objects in the electronics research field. Besides advanced engineering techniques, considering new material systems may be helpful. Here, we demonstrate two-dimensional(2D) subthermionic field-effect transistors(FETs) with sub-5 nm gate lengths based on ferroelectric(FE) van der Waals heterostructures(vdWHs).The FE vd WHs are composed of graphene, MoS2, and CuInP2S6 acting as 2D contacts, channels, and ferroelectric dielectric layers, respectively. We first show that the as-fabricated long-channel device exhibits nearly hysteresis-free subthermionic switching over three orders of magnitude of drain current at room temperature. Further, we fabricate short-channel subthermionic FETs using metallic carbon nanotubes as effective gate terminals. A typical device shows subthermionic switching over five-to-six orders of magnitude of drain current with a minimum subthreshold swing of 6.1 mV/dec at room temperature. Our results indicate that 2D materials system is promising for advanced highly-integrated energy-efficient electronic devices.

Robustly stable intermediate memory states in HfO_(2)-based ferroelectric field-effect transistors

Multilevel ferroelectric field-effect transistors(FeFETs)integrated with HfO_(2)-based ferroelectric thin films demonstrate tremendous potential in high-speed massive data storage and neuromorphic computing applications.However,few works have focused on the stability of the multiple memory states in the HfO_(2)-based FeFETs.Here we firstly report the write/read disturb effects on the multiple memory states in the Hf_(0.5)Zr_(0.5)O_(2)(HZO)-based FeFETs.The multiple memory states in HZO-based FeFETs do not show obvious degradation with the write and read disturb cycles.Moreover,the retention characteristics of the intermediate memory states in HZO-based FeFETs with unsaturated ferroelectric polarizations are better than that of the memory state with saturated ferroelectric polarization.Through the deep analysis of the operation principle of in HZO-based FeFETs,we speculate that the better retention properties of intermediate memory states are determined by the less ferroelectric polarization degradation and the weaker ferroelectric polarization shielding.The experimental and theoretical evidences confirm that the long-term stability of the intermediate memory states in HZO-based FeFETs are as robust as that of the saturated memory state,laying a solid foundation for their practical applications.

不同厚度铁电薄膜的制备及15nm Hf_(0.5)Zr_(0.5)O_(2)铁电晶体管性能研究

在铁电场效应晶体管(Ferroelectric Field Effect Transistor,FeFET)中,Hf_(0.5)Zr_(0.5)O_(2)(HZO)铁电薄膜的厚度是影响晶体管性能的关键参数。通过制备不同厚度铁电薄膜的铁电电容对其进行测试,选择最优厚度的铁电薄膜,设计制备一种15 nm Hf_(0.5)Zr_(0.5)O_(2)铁电薄膜的铁电晶体管——Si/HZO/W(MFS)栅极结构的铁电晶体管。它的剩余极化强度2Pr达到30μC·cm^(-2),具有高的循环稳定性和倍率性能,电压窗口达到1.2 V,在铁电存储器领域具有巨大的应用潜力。

HfO_(2)-based ferroelectric thin film and memory device applications in the post-Moore era:A review

The rapid development of 5G,big data,and Internet of Things(IoT)technologies is urgently required for novel non-volatile memory devices with low power consumption,fast read/write speed,and high reliability,which are crucial for high-performance computing.Ferroelectric memory has undergone extensive investigation as a viable alternative for commercial applications since the post-Moore era.However,conventional perovskite-structure ferroelectrics(e.g.,PbZr_(x)Ti_(1-x)O_(3))encounter severe limitations for high-density integration owing to the size effect of ferroelectricity and incompatibility with complementary metal-oxide-semiconductor technology.Since 2011,the ferroelectric field has been primarily focused on HfO_(2)-based ferroelectric thin films owing to their exceptional scalability.Several reviews discussing the control of ferroelectricity and device applications exist.It is believed that a comprehensive understanding of mechanisms based on industrial requirements and concerns is necessary,such as the wake-up effect and fatigue mechanism.These mechanisms reflect the atomic structures of the materials as well as the device physics.Herein,a review focusing on phase stability and domain structure is presented.In addition,the recent progress in related ferroelectric memory devices and their challenges is briefly discussed.

Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric

Analytical models are presented for a negative capacitance double-gate tunnel field-effect transistor（NC DG TFET） with a ferroelectric gate dielectric in this paper. The model accurately calculates the channel potential profile by solving the Poisson equation with the Landau-Khalatnikov（LK） equation. Moreover, the effects of the channel mobile charges on the potential are also taken into account. We also analyze the dependences of the channel potential and the on-state current on the device parameters by changing the thickness of ferroelectric layer,ferroelectric material and also verify the simulation results accord with commercial TCAD. The results show that the device can obtain better characteristics when the thickness of the ferroelectric layer is larger as it can reduce the shortest tunneling length.

基于铁电晶体管的存储与存算一体电路

近年来,物联网和人工智能等技术的发展对片上存储与智能计算的能效、密度以及性能提出了更高的要求。面对传统CMOS处理器的能效与密度瓶颈,以及传统冯·诺伊曼架构的“存储墙”瓶颈,以铁电晶体管(FeFET)为代表的新型非易失存储器(NVM)提供了新的机遇。FeFET具有非易失、高能效、高开关比等特点,非常适合低功耗、高密度场景下的存储与存算一体(CiM)应用,为数据密集型应用在边缘端的部署提供支持。该文回顾了FeFET的发展历程、结构、特性以及建模相关的工作,概述了FeFET存储器在电路结构和访存机制上的探索与优化。进一步地,该文还探讨了FeFET CiM在非易失计算、存内逻辑计算、矩阵向量乘法以及内容可寻址存储器上的应用。最后,该文从不同方面分析并展望了基于FeFET的存储与CiM电路的前景与挑战。

铁电晶体管近似搜索存储器的电流模测量实现

在高硬件容错性模型中,近似搜索可应对数据量与运算量需求能效提高的问题.针对三态内容寻址存储器在近似搜索模式下精度低、可扩展性差等问题,提出了一种电流模测量方案.该方案基于铁电晶体管优化了存储单元的结构设计以降低面积与功耗;将阵列搜索不匹配度由原先的电压输出改为电流输出,提高了电路可扩展性;引入了将模拟电流信号转化为数字脉冲信号的感测放大器(sense amplifier,SA)作为外围电路以检测存储阵列的不匹配度输出.通过Hspice与Virtuoso仿真平台搭建瞬态仿真电路实验,验证了该方案成功地实现了高能效三态内容寻址存储器近似搜索.

铁电场效应晶体管材料设计的研究进展

铁电场效应晶体管(FeFET)作为最有潜力的下一代非易失性存储器之一,引起研究人员的广泛关注。本文系统阐述了Fe FET的工作原理及结构设计,介绍了Fe FET结构中铁电材料和缓冲层材料的探索历程及所对应的器件性能。本文提出了一种新型Fe FET结构设计,有望改善薄膜之间的界面效应。最后总结了Fe FET的研究进展,并对未来研究做出展望。

铁电场效应晶体管

介绍了铁电场效应晶体管 (FFET)的基本结构、存储机制、制作方法 ,综述其结构设计的改进、铁电薄膜在 FFET中应用的进展情况 ,探讨围绕铁电薄膜材料、过渡层、结构设计、不同成膜方法及工艺对 FFET存储特性的影响 ,对