We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage）...We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.展开更多
Solution-processed n-type organic semiconductor micro/nanocrystals （OSMCs） are fundamental elements for developing low-cost, large-area, and all organic logic/complementary circuits. However, the development of air-...Solution-processed n-type organic semiconductor micro/nanocrystals （OSMCs） are fundamental elements for developing low-cost, large-area, and all organic logic/complementary circuits. However, the development of air-stable, highly aligned n-channel OSMC arrays for realizing high-performance devices lags far behind their p-channel counterparts. Herein, we present a simple one-step slope-coating method for the large-scale, solution-processed fabrication of highly aligned, air-stable, n-channel ribbon-shaped single-crystalline N,N＇-bis（2- phenylethyl）-perylene-3,4：9,10-tetracarboxylic diimide （BPE-PTCDI） arrays. The slope and pattemed photoresist （PR） stripes on the substrate are found to be crucial for the formation of large-area submicron ribbon arrays. The width and thickness of the BPE-PTCDI submicron ribbons can be finely tuned by controlling the solution concentration as well as the slope angle. The resulting BPE-PTCDI submicron ribbon arrays possess an optimum electron mobility up to 2.67 cm2.V-l.s-1 （with an average mobility of 1.13 cm2.V-l-s-1）, which is remarkably higher than that of thin film counterparts and better than the performance reported previously for single-crystalline BPE-PTCDI-based devices. Moreover, the devices exhibit robust air stability and remain stable after exposing in air over 50 days. Our study facilitates the development of air-stable, n-channel organic field-effect transistors （OFETs） and paves the way towards the fabrication of high-performance, organic single crystal-based integrated circuits.展开更多
The chemical vapor deposition （CVD） of graphene on Cu substrates enables the fabrication of large-area monolayer graphene on desired substrates. However, during the transfer of the synthesized graphene, topographic ...The chemical vapor deposition （CVD） of graphene on Cu substrates enables the fabrication of large-area monolayer graphene on desired substrates. However, during the transfer of the synthesized graphene, topographic defects are unavoidably formed along the Cu grain boundaries, degrading the electrical properties of graphene and increasing the device-to-device variability. Here, we introduce a method of hot-pressing as a surface pre-treatment to improve the thermal stability of Cu thin film for the suppression of grain boundary grooving. The flattened Cu thin film maintains its smooth surface even after the subsequent high temperature CVD process necessary for graphene growth, and the formation of graphene without wrinkles is realized. Graphene field effect transistors （FETs） fabricated using the graphene synthesized on hot-pressed Cu thin film exhibit superior field effect mobility and significantly reduced device-to-device variation.展开更多
For the development of ultra-sensitive electrical bio/chemical sensors based on nanowire field effect transistors （FETs）, the influence of the ions in the solution on the electron transport has to be understood. For...For the development of ultra-sensitive electrical bio/chemical sensors based on nanowire field effect transistors （FETs）, the influence of the ions in the solution on the electron transport has to be understood. For this purpose we establish a simulation platform for nanowire FETs in the liquid environment by implementing the modified Poisson-Boltzmann model into Landauer transport theory. We investigate the changes of the electric potential and the transport characteristics due to the ions. The reduction of sensitivity of the sensors due to the screening effect from the electrolyte could be successfully reproduced. We also fabricated silicon nanowire Schottky-barrier FETs and our model could capture the observed reduction of the current with increasing ionic concentration. This shows that our simulation platform can be used to interpret ongoing experiments, to design nanowire FETs, and it also gives insight into controversial issues such as whether ions in the buffer solution affect the transport characteristics or not.展开更多
提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势...提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.展开更多
This paper describes the definition of the complete transistor.For semiconductor devices,the complete transistor is always bipolar,namely,its electrical characteristics contain both electron and hole currents controll...This paper describes the definition of the complete transistor.For semiconductor devices,the complete transistor is always bipolar,namely,its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions.Partially complete or incomplete transistors,via coined names or/and designed physical geometries,included the 1949 Shockley p/n junction transistor（later called Bipolar Junction Transistor,BJT）,the 1952 Shockley unipolar ＇field-effect＇ transistor（FET,later called the p/n Junction Gate FET or JGFET）,as well as the field-effect transistors introduced by later investigators.Similarities between the surface-channel MOS-gate FET（MOSFET） and the volume-channel BJT are illustrated.The bipolar currents,identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base,led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices,and also the importance of the terminal contacts.展开更多
文摘We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.
文摘Solution-processed n-type organic semiconductor micro/nanocrystals （OSMCs） are fundamental elements for developing low-cost, large-area, and all organic logic/complementary circuits. However, the development of air-stable, highly aligned n-channel OSMC arrays for realizing high-performance devices lags far behind their p-channel counterparts. Herein, we present a simple one-step slope-coating method for the large-scale, solution-processed fabrication of highly aligned, air-stable, n-channel ribbon-shaped single-crystalline N,N＇-bis（2- phenylethyl）-perylene-3,4：9,10-tetracarboxylic diimide （BPE-PTCDI） arrays. The slope and pattemed photoresist （PR） stripes on the substrate are found to be crucial for the formation of large-area submicron ribbon arrays. The width and thickness of the BPE-PTCDI submicron ribbons can be finely tuned by controlling the solution concentration as well as the slope angle. The resulting BPE-PTCDI submicron ribbon arrays possess an optimum electron mobility up to 2.67 cm2.V-l.s-1 （with an average mobility of 1.13 cm2.V-l-s-1）, which is remarkably higher than that of thin film counterparts and better than the performance reported previously for single-crystalline BPE-PTCDI-based devices. Moreover, the devices exhibit robust air stability and remain stable after exposing in air over 50 days. Our study facilitates the development of air-stable, n-channel organic field-effect transistors （OFETs） and paves the way towards the fabrication of high-performance, organic single crystal-based integrated circuits.
文摘The chemical vapor deposition （CVD） of graphene on Cu substrates enables the fabrication of large-area monolayer graphene on desired substrates. However, during the transfer of the synthesized graphene, topographic defects are unavoidably formed along the Cu grain boundaries, degrading the electrical properties of graphene and increasing the device-to-device variability. Here, we introduce a method of hot-pressing as a surface pre-treatment to improve the thermal stability of Cu thin film for the suppression of grain boundary grooving. The flattened Cu thin film maintains its smooth surface even after the subsequent high temperature CVD process necessary for graphene growth, and the formation of graphene without wrinkles is realized. Graphene field effect transistors （FETs） fabricated using the graphene synthesized on hot-pressed Cu thin film exhibit superior field effect mobility and significantly reduced device-to-device variation.
文摘For the development of ultra-sensitive electrical bio/chemical sensors based on nanowire field effect transistors （FETs）, the influence of the ions in the solution on the electron transport has to be understood. For this purpose we establish a simulation platform for nanowire FETs in the liquid environment by implementing the modified Poisson-Boltzmann model into Landauer transport theory. We investigate the changes of the electric potential and the transport characteristics due to the ions. The reduction of sensitivity of the sensors due to the screening effect from the electrolyte could be successfully reproduced. We also fabricated silicon nanowire Schottky-barrier FETs and our model could capture the observed reduction of the current with increasing ionic concentration. This shows that our simulation platform can be used to interpret ongoing experiments, to design nanowire FETs, and it also gives insight into controversial issues such as whether ions in the buffer solution affect the transport characteristics or not.
文摘提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.
基金supported by the CTSAH Associates(CTSA)founded by the late Linda Su-Nan Chang Sah,in memory of her 70th anniversary. The content of this article was presented as the conference opening keynote by Jie Binbin at the Work-shop on Compact Modeling on May 5, 2009 in Houston, Texas, USA
文摘This paper describes the definition of the complete transistor.For semiconductor devices,the complete transistor is always bipolar,namely,its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions.Partially complete or incomplete transistors,via coined names or/and designed physical geometries,included the 1949 Shockley p/n junction transistor（later called Bipolar Junction Transistor,BJT）,the 1952 Shockley unipolar ＇field-effect＇ transistor（FET,later called the p/n Junction Gate FET or JGFET）,as well as the field-effect transistors introduced by later investigators.Similarities between the surface-channel MOS-gate FET（MOSFET） and the volume-channel BJT are illustrated.The bipolar currents,identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base,led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices,and also the importance of the terminal contacts.
