一款基于新型Field Programmable Gate Array芯片的投影仪梯形校正系统研究与实现

投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(Field Programmable Gate Array)芯片的新型梯形校正实现方案,解决了校正范围与锯齿失真的矛盾问题,并为进一步成为芯片级产品铺平了道路.图像处理采用kaiser窗函数和sinc函数相结合的方法进行插值,这样的滤波器改善了旁瓣抑制,具有较好的通带性能.介绍了梯形失真的产生和校正原理,提出了利用FPGA芯片XC3S400作为核心图像处理单元的梯形校正系统的硬件和软件实现,说明了该芯片结构、功能及特性,最后提供了校正的效果图.

A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array

A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.

Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA)

An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.

Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software

In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.

Implimentations of SIMD machine using programmable gate array

Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

Implementation of Synchronization Technology in Orthogonal Frequency Division Multiplex System Based on Field Programming Gate Array

In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.

X-Debugger:基于FPGA的扫描调试器设计及实现

针对芯片硅后调试面临内部信号可观测性差、可控制性弱、内部状态不易恢复重建等问题,本文设计和实现了一款基于现场可编程门阵列(FPGA)的快速扫描调试器XDebugger。该调试器复用传统可测试设计(DFT)扫描链路逻辑,在芯片的设计阶段插入基于功能模块前导码的扫描控制电路,实现了芯片内部各数字逻辑模块信号100%可见;通过基于FPGA的扫描调试器X-Debugger可以快速完成芯片内部寄存器状态获取和修改,并结合硬件加速器可以完成芯片内部逻辑状态的快速重建,从而形成硅后调试闭环。在某处理器芯片硅后调试实践中的结果表明,对于小于100万触发器的功能模块可以在1 s内完成内部状态获取、修改和重建,全芯片通过X-Debugger内部信号获取和重建小于1 min,极大提高了该处理器芯片的硅后调试效率。

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

ARM+FPGA双核计算的配电自动化终端设计

为了提高配电自动化终端数据信息自动化分析能力,设计了基于ARM+现场可编程门阵列(FPGA)双核计算的配电自动化终端。为了提高模块计算能力,在模块中构建了堆叠式自动编码器-神经网络(SAE-NN)深度学习算法模型。在常规堆叠式自动编码器(SAE)深度学习模型基础上融合神经网络(NN)模型,应用过程中改善传统NN对分层节点数目的限制。试验结果表明,所设计终端随着系统运行能达到95%以上的精度,而现有SAE模型仅达到85%左右的精度。通过与文献[1]和文献[2]方法的对比可知,所设计终端有较高的调度能力。该设计显著提高了配电网数据信息的分析精度,大幅提升了电网应用对数据信息处理的准确度和效率。

大尺寸机载显示模块动态背光控制系统设计

机载大尺寸液晶显示器(liquid crystal display,LCD)显示模块具有亮度高和功耗大的特点。为了降低其动态功耗,介绍了一种用于大尺寸机载显示模块的动态背光控制系统。该系统采用发光二极管(light emitting diode,LED)动态背光控制技术,通过对背光的动态调节,提高动态显示效果和达到节能的目的。对系统的硬件电路和软件设计算法进行了详细的介绍,并进行实验验证。结果表明,该系统能够有效地提高机载显示模块的动态显示效果,并显著降低了动态功耗。

GJB 5000B在FPGA工程中的应用分析

为引入软件工程化管理办法对设计开发实践实施管理,结合GJB 5000B体系要求,对现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的设计开发流程和GJB 5000B的工程实践要求进行梳理、比对和分析,并提出一套FPGA开发管理在GJB 5000B推进实践中的实施办法。研究成果可为GJB 5000B在FPGA工程中的应用提供一定参考。

FPGA-Based Efficient Programmable Polyphase FIR Filter

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)

Development of a Wireless Capsule Endoscope System Based on Field Programmable Gate Array

A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform, uniform quantization, sub-sampling, differential pulse code modulation (DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array (FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio (PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details. © 2017, Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg.

Implementation of Dynamic Matrix Control on Field Programmable Gate Array

High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.

An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays

We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages,and more parallel units within a stage.It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs),and can be well matched to the placement of the resources on the FPGA.We adopt the decimation-infrequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA.Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz.

高分辨中子闪烁体探测器读出电子学研制

能量分辨中子成像谱仪是中国散裂中子源当前在建的谱仪之一,其衍射探测器90°分区采用6LiF/ZnS中子闪烁体探测器作为探测设备。为实现探测器高位置分辨,读出电子学系统采用了一种电容网络复合读出电路和电荷重心法相结合的实现方法,并研制了电子学样机。该样机由电容网络复合读出电路、前置放大板和数字读出板三部分组成,基本功能验证完成后,分别在实验室和中国散裂中子源的20号束线上进行了相关性能参数测试,测试结果显示:电子学的积分非线性≤0.95%,时间分辨约为12 ns;探测器位置分辨为1 mm、探测效率为65%@1.6?,均达到了工程设计指标。该样机的成功研制为能量分辨中子成像谱仪未来顺利开展谱仪实验提供了可靠的技术保障。

基于FPGA的埋地钢质管道牺牲阳极智能阴极保护系统研制

为实现埋地钢质管道阴极保护状态的远程监测,基于FPGA技术提出了一种埋地钢质管道牺牲阳极智能阴极保护系统设计方法。现场可编程门阵列(FPGA)作为并行处理单元实现阴极保护参数的采集。采用无线4G和以太网2种高速通讯方式用于远程实时监控和本地数据重复读取,解决了因网络中断导致的数据丢失问题。实验结果表明:设计的智能阴极保护系统具有采集准确、存储可靠、监控及时的特点,能够满足现场工程应用的需求。

基于FPGA的远程快速在线升级技术研究

现场可编程门阵列(FPGA)在电子对抗领域如多通道数字接收机、波束合成阵列中大量应用,使用现有的JTAG调试器对其进行升级非常耗费时间。基于可执行文件对FPGA进行Multiboot配置,将FLASH配置区域进行自定义分区规划,通过千兆以太网对多块FPGA完成远程在线升级。该方法简化了配置链路,降低了配置复杂度,提升了配置速度;使用网线远程完成任务,省去了分批多次配置时需在多块板卡上进行拔插的复杂流程,克服了已列装设备在地理位置和结构上的诸多不便;具有校验回退机制,保证了配置安全。