A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

Machine learning algorithm partially reconfigured on FPGA for an image edge detection system

Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.

大尺寸机载显示模块动态背光控制系统设计

机载大尺寸液晶显示器(liquid crystal display,LCD)显示模块具有亮度高和功耗大的特点。为了降低其动态功耗,介绍了一种用于大尺寸机载显示模块的动态背光控制系统。该系统采用发光二极管(light emitting diode,LED)动态背光控制技术,通过对背光的动态调节,提高动态显示效果和达到节能的目的。对系统的硬件电路和软件设计算法进行了详细的介绍,并进行实验验证。结果表明,该系统能够有效地提高机载显示模块的动态显示效果,并显著降低了动态功耗。

GJB 5000B在FPGA工程中的应用分析

为引入软件工程化管理办法对设计开发实践实施管理,结合GJB 5000B体系要求,对现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的设计开发流程和GJB 5000B的工程实践要求进行梳理、比对和分析,并提出一套FPGA开发管理在GJB 5000B推进实践中的实施办法。研究成果可为GJB 5000B在FPGA工程中的应用提供一定参考。

FPGA-Based Efficient Programmable Polyphase FIR Filter

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)

Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH

This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.

Implementation of Dynamic Matrix Control on Field Programmable Gate Array

High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA.

Development of a Wireless Capsule Endoscope System Based on Field Programmable Gate Array

A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform,uniform quantization, sub-sampling, differential pulse code modulation(DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array(FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio(PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details.

An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays

We present a novel method to implement the radix-2 fast Fourier transform (FFT) algorithm on field programmable gate arrays (FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages,and more parallel units within a stage.It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines (GBEs),and can be well matched to the placement of the resources on the FPGA.We adopt the decimation-infrequency (DIF) radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA.Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11 μs with a clock frequency of 200 MHz.

Principle and architecture of parallel reconfiguration circuit for ternary optical computer

Reconfiguration is the key to produce an applicable ternary optical computer （TOC）. The method to implement the reconfiguration function determines whether a TOC can step into applied fields or not. In this work, a design of the reconfiguration circuit based on field programmable gates array （FPGA） is proposed, and the structure of the entire hardware system is discussed.

基于FPGA的控制算法定点化设计

运动控制算法在现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)上实现过程中,当数据类型由浮点转定点时,存在无法保证高精度的问题。为此使用simulink中的定点工具(Fixed-Point Tool)对算法内部各信号数据的范围进行分析,然后人为地对Fixed-Point Tool给出的建议位宽进行修正,从而使算法在保证较高精度的同时,也解决了采用统一较长位宽在FPGA上实现时造成的资源浪费问题。与传统的人为定义数据位宽相比,使用Fixed-Point Tool设置数据位宽,在输入数据范围发生变化时,能够更加灵活、动态地调整算法内部数据位宽。

双磁控忆阻器动力学模型及FPGA硬件电路实现

基于经典Chua混沌电路设计了一个五维双磁控忆阻器混沌电路。对电路非线性特性进行数值分析,表明其具有丰富的混沌动力学行为。采用一阶离散处理对电路进行数字化转换,基于DSP Builder和FPGA(Field Programmable Gate Array)技术,通过CycloneⅣE系列EP4CE10F17C8N芯片搭建的硬件平台,真实实现了该模型数字化系统。设计结果表明,数字化忆阻器系统避免了模拟信号元器件的漂移和不稳定性,硬件波形显示性能稳定可靠,且与计算机仿真结果具有相当一致性的吻合。

REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES

Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.

Design and Implementation of a Novel HomePlug-Based Solution for Low Cost and High Performance Smart Home Networking

As the smart home is the end-point power consumer, it is the major part to be controlled in a smart micro grid. There are so many challenges for implementing a smart home system in which the most important ones are the cost and simplicity of the implementation method. It is clear that the major share of the total cost is referred to the internal controlling system network; although there are too many methods proposed but still there is not any satisfying method at the consumers＇ point of view. In this paper, a novel solution for this demand is proposed, which not only minimizes the implementation cost, but also provides a high level of reliability and simplicity of operation; feasibility, extendibility, and flexibility are other leading properties of the design.

Research and test of the adaptive quadrature demodulation technology for silicon micro-machined gyroscope

A program of adaptive quadrature demodulation is proposed to supply the gaps in the traditional analog detection technology of a silicon micro-machined gyroscope (SMG). This program is suitable for digital phase locked loop (DPLL) drive technology that proposed in other papers. In addition the program adopts an adaptive filtering algorithm, which selects the in-phase and quadrature components that are outputs of the DPLL of the SMG's drive mode as reference signals to update the amplitude of the in-phase and quadrature components of the input signal by iteratively. An objective of the program is to minimize the mean square error of the accurate amplitudes and the estimated amplitudes of SMG's detection mode. The simulation and test results prove the feasibility of the program that lays the foundation for the further improvement of the SMG's system performance and the implementation of the SMG system's self-calibration and self-demarcation in future.

Implementation of access controller for Ethernet passive optical network

This paper presents the design and implementation of access controller used for Ethernet passive optical network （ EPON）. As a first step to develop an ASIC product, the entire system is designed on a field programmable gate array （FPGA） with an embedded CPU. To reduce working frequency of the FPGA, the byte-to-word conversion is proposed. Propagation delays are equalized by ranging procedure so as to avoid data collision. Implementations of synchronization, classification, as well as Linux porting are illustrated in detail. The interface between the FPGA and CPU are also presented. Experimental results show that the proposed system can properly function in a relatively low cost FPGA.

基于Xilinx型FPGA系统单粒子效应评估方法研究

Virtex-5系列芯片没有官方提供的专用软错误缓解(Soft Error Mitigation,SEM)IP核,需自行设计故障注入系统.本文选用XC5VFX130T型现场可编程门阵列(Field Programmable Gate Array,FPGA)芯片利用单帧部分重构功能达到等同于SEM IP故障注入效果,实现对FPGA电路系统的抗单粒子翻转能力评估测试.利用逐位注入故障模式对XC5VFX130T型FPGA的配置位逐个注入故障,获得待评估电路的敏感配置位信息;对待测电路进行三模冗余防护加固,利用累积故障注入模式连续随机注入模拟单粒子辐照试验环境,得到待评估电路的功能中断截面,进而实现对基于XC5VFX130T型FPGA系统的抗单粒子翻转加固效果的评估.研究表明,基准电路(移位寄存器链等)评估得到的功能中断截面与实际辐照试验中的功能中断截面曲线变化一致,为机载电子的单粒子效应适航评估提供了支持.

A multi-directional controllable multi-scroll conservative chaos generator:Modelling,analysis,and FPGA implementation

Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption.

Fault Tolerant Reconfigurable System with Dual-Module Redundancy and Dynamic Reconfiguration

To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable technique of field programmable gate array（FPGA）. This system contains detection and backup alternative functions,that is,the self-detection and self-healing functions can be completed,and consequently a system design with low hardware redundancy and high resource utilization can be achieved successfully. So it can not only detect fault but also repair the fault effectively after failure. Hence,this method is especially practical to the dynamically reconfigurable computers based on FPGAs. Design methodology has been verified by Virtex-4 FPGA on Xilinx Ml403 development platform.