Temperature and drain bias dependence of single event transient in 25-nm FinFET technology

In this paper, we investigate the temperature and drain bias dependency of single event transient （SET） in 25-nm fin field-effect-transistor （FinFET） technology in a temperature range of 0-135 ℃ and supply voltage range of 0.4 V- 1.6 V. Technology computer-aided design （TCAD） three-dimensional simulation results show that the drain current pulse duration increases from 0.6 ns to 3.4 ns when the temperature increases from 0 to 135 ℃. The charge collected increases from 45.5 ℃ to 436.9 fC and the voltage pulse width decreases from 0.54 ns to 0.18 ns when supply voltage increases from 0.4 V to 1.6 V. Furthermore, simulation results and the mechanism of temperature and bias dependency are discussed.

Analytical capacitance model for 14 nm Fin FET considering dual-k spacer

The conformal mapping of an electric field has been employed to develop an accurate parasitic capacitance model for nanoscale fin field-effect transistor（Fin FET） device. Firstly, the structure of the dual-layer spacers and the gate parasitic capacitors are thoroughly analyzed. Then, the Cartesian coordinate is transferred into the elliptic coordinate and the equivalent fringe capacitance model can be built-up by some arithmetical operations. In order to validate our proposed model, the comparison of statistical analysis between the proposed calculation and the 3D-TCAD simulation has been carried out, and several different material combinations of the dual-k structure have been considered. The results show that the proposed analytical model can accurately calculate the fringe capacitance of the Fin FET device with dual-k spacers.

Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.

垂直氮化镓鳍式功率场效应晶体管优化设计

主要研究了垂直氮化镓鳍式功率场效应晶体管的器件特性。利用理论计算和器件模拟,系统地设计和优化了n型氮化镓漂移层的掺杂浓度和厚度以及鳍宽度的参数,使得击穿电压和导通电阻达到最佳的折衷。经过最终优化后,当n型氮化镓漂移层的掺杂浓度、漂移层的厚度、鳍宽度分别为5×10^(15)cm^(-3)、10μm、0.2μm时,得到高击穿电压为1150 V、低导通电阻为1.01 mΩ·cm^(2)、高Baliga优值为1.31 GW/cm^(2)。结果表明,通过本文方法优化的垂直氮化镓鳍式功率场效应晶体管可用于大功率和高压场合。

Performance projections for ballistic carbon nanotube FinFET at circuit level

A novel three-dimensional device structure for a carbon nanotube （CNT） fin field-effect transistor （FinFET） is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product （EDP）. Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage （V~ = 1/3Vaa）. A suitable improvement in Vth can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage （Vdd -- 0.4 V）, suggesting great potential for CNT FinFET-based integrated circuits.