This article deals with two important issues in digital filter implementation： roundoff noise and limit cycles. A novel class of robust state-space realizations, called normal realizations, is derived and characteriz...This article deals with two important issues in digital filter implementation： roundoff noise and limit cycles. A novel class of robust state-space realizations, called normal realizations, is derived and characterized. It is seen that these realizations are free of limit cycles. Another interesting property of the normal realizations is that they yield a minimal error propagation gain. The optimal realization problem, defined as to find those normal realizations that minimize roundoff noise gain, is formulated and solved analytically. A design example is presented to demonstrate the behavior of the optimal normal realizations and to compare them with several well-known digital filter realizations in terms of minimizing the roundoff noise and the error propagation.展开更多
The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom...The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.展开更多
为解决传统数字滤波器在有限精度实现时因有限字长(Finite Word Length,FWL)效应导致滤波器性能下降的问题,提出一种L_(2)灵敏度最小化的数字滤波器状态空间实现稀疏化方法.推导前向差分算子数字滤波器结构传输函数及其等效状态空间实现...为解决传统数字滤波器在有限精度实现时因有限字长(Finite Word Length,FWL)效应导致滤波器性能下降的问题,提出一种L_(2)灵敏度最小化的数字滤波器状态空间实现稀疏化方法.推导前向差分算子数字滤波器结构传输函数及其等效状态空间实现,根据可控及可观格莱姆矩阵得到基于相似变换矩阵的L_(2)灵敏度表达式,并进行稀疏化校准,将L_(2)灵敏度最小化问题转换为凸函数求最值问题,求导得到L_(2)灵敏度最小化表达式,代回即得前向差分算子数字滤波器的稀疏化状态空间实现.仿真结果表明,所提方法设计的数字滤波器具有更好的抗FWL效应.展开更多
ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to ...ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.展开更多
基金the National Nature Science Foundation of China (60774021)
文摘This article deals with two important issues in digital filter implementation： roundoff noise and limit cycles. A novel class of robust state-space realizations, called normal realizations, is derived and characterized. It is seen that these realizations are free of limit cycles. Another interesting property of the normal realizations is that they yield a minimal error propagation gain. The optimal realization problem, defined as to find those normal realizations that minimize roundoff noise gain, is formulated and solved analytically. A design example is presented to demonstrate the behavior of the optimal normal realizations and to compare them with several well-known digital filter realizations in terms of minimizing the roundoff noise and the error propagation.
基金Supported by the Funds for Creative Research Groups of China 60521003）, the State Key Program of National Natural Science of ina （60534010）, National Natural Science Foundation of China （60674021）, the Funds of Ph.D. Program of Ministry of Eduction, China （20060145019）, and the 111 Project （B08015）
文摘过滤有限的词长度(FWL ) 为线性分离时间的系统影响的问题的 nonfragile H 在这份报纸被调查。要设计的过滤器被假定与添加剂获得变化，它在过滤器实现上反映 FWL 效果。结构化的顶点隔板的一个观点被建议处理这个问题并且利用了以一套线性矩阵不平等(LMI ) 为 nonfragile H 过滤器设计开发足够的条件。设计使扩充系统变为 asymptotically 稳定并且保证 H 变细水平不到规定水平。一个数字例子被给说明建议方法的效果。
文摘The closed-loop stability issue of finite-precision realizations was investigated for digital control-lers implemented in block-floating-point format. The controller coefficient perturbation was analyzed resultingfrom using finite word length (FWL) block-floating-point representation scheme. A block-floating-point FWL closed-loop stability measure was derived which considers both the dynamic range and precision. To facilitate the design of optimal finite-precision controller realizations, a computationally tractable block-floating-point FWL closed-loop stability measure was then introduced and the method of computing the value of this measure for a given controller realization was developed. The optimal controller realization is defined as the solution that maximizes the corresponding measure, and a numerical optimization approach was adopted to solve the resulting optimal realization problem. A numerical example was used to illustrate the design procedure and to compare the optimal controller realization with the initial realization.
文摘为解决传统数字滤波器在有限精度实现时因有限字长(Finite Word Length,FWL)效应导致滤波器性能下降的问题,提出一种L_(2)灵敏度最小化的数字滤波器状态空间实现稀疏化方法.推导前向差分算子数字滤波器结构传输函数及其等效状态空间实现,根据可控及可观格莱姆矩阵得到基于相似变换矩阵的L_(2)灵敏度表达式,并进行稀疏化校准,将L_(2)灵敏度最小化问题转换为凸函数求最值问题,求导得到L_(2)灵敏度最小化表达式,代回即得前向差分算子数字滤波器的稀疏化状态空间实现.仿真结果表明,所提方法设计的数字滤波器具有更好的抗FWL效应.
文摘ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise： in control system and hardware design. In this paper, we only focus on the hardware side of the problem. We show how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms： Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer4evel （RTL） level as technology-independent reusable IP-cores. They are reconfigurable according to two compilemtime constants： set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.
