High-speed, high-accuracy data converters are attractive for use in most RF applications. Such converters allow direct conversion to occur between the digital baseband and the antenna. However, high speed and high acc...High-speed, high-accuracy data converters are attractive for use in most RF applications. Such converters allow direct conversion to occur between the digital baseband and the antenna. However, high speed and high accuracy make the analog components in a converter more complex, and this complexity causes more power to be dissipated than if a traditional approach were taken. A static calibration technique for flash analog-to-digital converters （ADCs） is discussed in this paper. The calibration is based onhistogram test methods, and equivalent errors in the flash ADC comparators are estimated in the digital domain without any significant changes being made to the ADC comparators. In the trimming process, reference voltages are adjusted to compensate for static errors. Behavioral-level simulations of a moderate-resolution 8-bit flash ADC show that, for typical errors, ADC performance is considerably improved by the proposed technique. As a result of calibration, the differential no.nlinearities （DNLs） are reduced on average from 4 LSB to 0.5 LSB, and the integral nonlinearities （INLs） are reduced on average from 4.2 LSB to 0.35 LSB. Implementation issues for this proposed technique are discussed in our subsequent paper, “A Histogram-Based Static-Error Correction Technique for Flash ADCs： Implementation Aspects. ”展开更多
In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters （ADCs）. In [1], we theoretically describ the calibration techniqu...In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters （ADCs）. In [1], we theoretically describ the calibration technique and perform a behaviorallevel simulation to test its functionality [1]. In this work, we discuss some issues in transistorlevel implementation. The predominant factors that contribute to static errors such as reference generator mismatch and trackandhold （T/H） gain error can be treated as inputreferred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistorlevel implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.展开更多
This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common inp...This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.展开更多
A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address ...A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.展开更多
A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-samplin...A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.展开更多
We report a high-speed flash analog to digital converter（ADC） linearization technique employing the inverse Volterra model and digital post processing.First,a 1.25 GS/s 5-bit flash ADC is designed using a 0.18μm CM...We report a high-speed flash analog to digital converter（ADC） linearization technique employing the inverse Volterra model and digital post processing.First,a 1.25 GS/s 5-bit flash ADC is designed using a 0.18μm CMOS,and the signal is quantized by a distributed track-and-hold circuit.Second,based on the Volterra series, a proposed digital post-calibration model is introduced.Then,the model is applied to estimate and compensate the nonlinearity of the high-speed flash ADC.Simulation results indicate that the distortion is reduced effectively. Specifically,the ADC achieves gains of 4.83 effective bits for a 117.1 MHz frequency input and 4.74 effective bits for a Nyquist input at 1.25 GS/s.展开更多
This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of t...This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.展开更多
文摘High-speed, high-accuracy data converters are attractive for use in most RF applications. Such converters allow direct conversion to occur between the digital baseband and the antenna. However, high speed and high accuracy make the analog components in a converter more complex, and this complexity causes more power to be dissipated than if a traditional approach were taken. A static calibration technique for flash analog-to-digital converters （ADCs） is discussed in this paper. The calibration is based onhistogram test methods, and equivalent errors in the flash ADC comparators are estimated in the digital domain without any significant changes being made to the ADC comparators. In the trimming process, reference voltages are adjusted to compensate for static errors. Behavioral-level simulations of a moderate-resolution 8-bit flash ADC show that, for typical errors, ADC performance is considerably improved by the proposed technique. As a result of calibration, the differential no.nlinearities （DNLs） are reduced on average from 4 LSB to 0.5 LSB, and the integral nonlinearities （INLs） are reduced on average from 4.2 LSB to 0.35 LSB. Implementation issues for this proposed technique are discussed in our subsequent paper, “A Histogram-Based Static-Error Correction Technique for Flash ADCs： Implementation Aspects. ”
文摘In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters （ADCs）. In [1], we theoretically describ the calibration technique and perform a behaviorallevel simulation to test its functionality [1]. In this work, we discuss some issues in transistorlevel implementation. The predominant factors that contribute to static errors such as reference generator mismatch and trackandhold （T/H） gain error can be treated as inputreferred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistorlevel implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.
文摘This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.
文摘A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V.
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University
文摘A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.
基金supported by the Microelectronics Laboratory,Department of Science and Electronics,Beijing Institute of Technology,and the Photonics Laboratory,Department of Electrical Engineering,University of California-Los Angeles
文摘We report a high-speed flash analog to digital converter（ADC） linearization technique employing the inverse Volterra model and digital post processing.First,a 1.25 GS/s 5-bit flash ADC is designed using a 0.18μm CMOS,and the signal is quantized by a distributed track-and-hold circuit.Second,based on the Volterra series, a proposed digital post-calibration model is introduced.Then,the model is applied to estimate and compensate the nonlinearity of the high-speed flash ADC.Simulation results indicate that the distortion is reduced effectively. Specifically,the ADC achieves gains of 4.83 effective bits for a 117.1 MHz frequency input and 4.74 effective bits for a Nyquist input at 1.25 GS/s.
文摘This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.
文摘时域延迟线架构ADC的非线性问题,导致其无法达到较高的分辨率。针对该问题,提出了一种将Flash和延迟线架构相结合的新型低功耗11位ADC。该新型混合ADC架构由两个模块构成,分别为4位Flash ADC架构和7位延迟线ADC架构,因此同时具有Flash ADC和延迟线ADC的准确性和高效性。采用CHARTERED 65 nm Dual Gate Mixed Signal CMOS Process设计并绘制出混合式ADC版图。实验测试结果显示,在供应电压为1.1 V和采样效率为100 Msample/s的条件下,混合式ADC产生的信噪失真比(SNDR)为60 d B,消耗功率为1.6 m W。在无需任何校准技术的情况下,混合式ADC产生的品质因数(FOM)为19.4 f J/分级转换。此外,利用不匹配的3σ设备进行了蒙特卡罗试验,结果表明,SNDR值低于其ADC架构。
