Novel p-Channel Selected n-Channel Divided Bit-Line NOR Flash Memory Using Source Induced Band-to-Band Hot Electron Injection Programming

A novel p-channel selected n-channel divided bit-line NOR(PNOR) flash memory,which features low programming current,low power,high access current,and slight bit-line disturbance,is proposed.By using the source induced band-to-band hot electron injection (SIBE) to perform programming and dividing the bit-line to the sub-bit-lines,the programming current and power can be reduced to 3.5μA and 16.5μW with the sub-bit-line width equaling to 128,and a read current of 60μA is obtained.Furthermore,the bit-line disturbance is also significantly alleviated.

A Novel Flash Memory Using Band-to-Band Tunneling Induced Hot Electron Injection to Program

A novel band to band hot electron programming flash memory device,which features programming with high speed,low voltage,low power consumption,large read current and short access time,is proposed.The new memory cell is programmed by band to band tunneling induced hot electron (BBHE) injection method at the drain,and erased by Fowler Nordheim tunneling through the source region.The work shows that the programming control gate voltage can be reduced to 8V,and the drain leakage current is only 3μA/μm.Under the proposed operating conditions,the program efficiency and the read current rise up to 4×10 -4 and 60μA/μm,respectively,and the program time can be as short as 16μs

Low Voltage Flash Memory Cells Using SiGe Quantum Dots for Enhancing F-N Tunneling

A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.

A Novel Non-Planar Cell Structure for Flash Memory

Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.

SCDI Flash Memory Device Ⅰ: Simulation and Analysis

Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...

SCDI Flash Memory Device Ⅱ:Experiments and Characteristics

Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.

Heavy ion induced upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory

Upset errors in 90-nm 64 Mb NOR-type floating-gate Flash memory induced by accelerated ^（129）Xe and ^（209）Bi ions are investigated in detail. The linear energy transfer covers the range from 50 to 99.8 Me V/（mg/cm^2）. When the memory chips are powered off during heavy ions irradiation, single-event-latch-up and single-event-function-interruption are excluded,and only 0-〉1 upset errors in the memory array are observed. These error bit rates seem very difficult to achieve and cannot be simply recovered based on the power cycle. The number of error bits shows a strong dependence on the linear energy transfer（LET）. Under room-temperature annealing conditions, the upset errors can be reduced by about two orders of magnitude using rewrite/reprogram operations, but they subsequently increase once again in a few minutes after the power cycle. High-temperature annealing can diminish almost all error bits, which are affected by the lower LET ^（129）Xe ions. The percolation path between the floating-gate（FG） and the substrate contributes to the radiation-induced leakage current, and has been identified as the root cause of the upset errors of the Flash memory array in this work.

适用于Flash Memory的负高压泵的实现

提出一种适用于单电源,低电压供电的FlashMemory的负高压电荷泵的实现方法。在分析传统电荷泵工作原理的基础上,结合Flash工作电压和参数要求,提出三阱工艺,无阈值损失的负高压电荷泵电路结构。最后在0.22!mFlash工艺下给出测试结果。

Flash Memory测试技术发展

从Flash memory测试技术的发展背景出发,论述了flash memory测试技术的发展现状以及前景。同时重点对Flash-march算法和BF&D算法进行了分析和评价。指出Flash memory的发展是以测试技术的发展为基础的,必须把Flash memory本身的发展和测试技术的发展综合考虑,才能有助于两者的协调发展。

Flash Memory作为数据存储器在E5中的应用

本文介绍了一种基于FLASH MEMORY的数据存储应用方法。详细阐述了使用E5CPU将FLASH MEMORY作为数据存储器的基本原理,着重分析了地址映射的过程,给出了相应的框图及关键的程序。

面向Flash Memory的高性能数据存储引擎的研究

传统的数据存储引擎对Flash Memory数据的修改是通过页内更新技术实现的,这将导致FlashMemory的性能下降及其磨损加剧。针对该问题,文章提出了一种面向Flash Memory的采用页外更新技术的多版本数据存储引擎MV4Flash。该数据存储引擎采用多版本存储和垃圾回收机制,所有数据的更新和修改都通过文件追加的方式进行,适应了Flash Memory先擦除后写入的特点,延长了设备寿命。采用NDBBench对该数据存储引擎进行测试的结果表明,MV4Flash与传统的InnoDB相比,事物处理性能有较大的提升,更适合于数据规模大、实时性要求高的应用系统。

低功耗高速擦写Flash Memory的研究

随着嵌入式系统和移动通信的发展及集成电路特征尺寸的减小,对低功耗和更快的擦写速度提出了新的要求。文章从传统Flash Memory的结构缺陷上分析,为降低功耗及提高擦写速度方面提出了改进方法,并介绍了Flash Memory技术的发展趋势。

Low-Complexity Detection and Decoding Scheme for LDPC-Coded MLC NAND Flash Memory

With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.

LDPC Coding Scheme for Improving the Reliability of Multi-Level-Cell NAND Flash Memory in Radiation Environments

Utilizing commercial off-the-shelf(COTS) components in satellites has received much attention due to the low cost. However, commercial memories suffer severe reliability problems in radiation environments. This paper studies the low-density parity-check(LDPC) coding scheme for improving the reliability of multi-level-cell(MLC) NAND Flash memory in radiation environments. Firstly, based on existing physical experiment works, we introduce a new error model for heavyion irradiations; secondly, we explore the optimization of writing voltage allocation to maximize the capacity of the storage channel; thirdly, we design the degree distribution of LDPC codes that is specially suitable for the proposed model; finally, we propose a joint detection-decoding scheme based on LDPC codes, which estimates the storage channel state and executes an adaptive log-likelihood ratio(LLR) calculation to achieve better performance. Simulation results show that, compared with the conventional LDPC coding scheme, the proposed scheme may almost double the lifetime of the MLC NAND Flash memory in radiation environments.

POS产品中Flash Memory和电池测试软件设计

随着移动计算技术的发展和移动信息交换的日益频繁,闪存(FlashMemory)和电池也成为这些产品中不可缺少的组成部分。描述了一种用于闪存和电池测试的具体设计方案,侧重测试软件部分,主要包括总体设计思想和软件规划指标;介绍了各模块工作原理,以及各主要芯片如KU80L188EC13、MBM30LV0064、XC9572XL等。

Flash Memory程序存储器实验的设计

介绍了FLASH存储器芯片W 29C011A的读写操作和软件数据保护方法,设计了基于51单片机实验系统的FLASH存储器实验项目,在不用编程器的条件下,利用FLASH存储器的ISP功能将机器码写入FLASH存储器芯片,实现程序存储器功能。

Random telegraph noise on the threshold voltage of multi-level flash memory

We investigate the impact of random telegraph noise（RTN） on the threshold voltage of multi-level NOR flash memory.It is found that the threshold voltage variation（？Vth） and the distribution due to RTN increase with the programmed level（Vth） of flash cells. The gate voltage dependence of RTN amplitude and the variability of RTN time constants suggest that the large RTN amplitude and distribution at the high program level is attributed to the charge trapping in the tunneling oxide layer induced by the high programming voltages. A three-dimensional TCAD simulation based on a percolation path model further reveals the contribution of those trapped charges to the threshold voltage variation and distribution in flash memory.

嵌入式Flash Memory Cell技术

本文分析了目前常用的快闪存储器(Flash Memory)存储单元结构,介绍了一种适用于嵌入的单元结构,存储器阵列设计、可靠性设计技术。

Temperature-insensitive reading of a flash memory cell

The temperature characteristics of the read current of the NOR embedded flash memory with a 1.5T-per-cell structure are theoretically analyzed and experimentally verified.We verify that for a cell programmed with a“10”state,the read current is either increasing,decreasing,or invariable with the temperature,essentially depending on the reading overdrive voltage of the selected bitcell,or its programming strength.By precisely controlling the programming strength and thus manipulating its temperature coefficient,we propose a new setting method for the reference cells that programs each of reference cells to a charge state with a temperature coefficient closely tracking tail data cells,thereby solving the current coefficient mismatch and improving the read window.

Program Error Mitigation in MLC NAND Flash Memory with Soft Decision Decoders

Benefiting from strong decoding capabilities,soft-decision decoding has been used to replace hard-decision decoding in various communication systems,and NAND flash memory systems are no exception.However,soft-decision decoding relies heavily on accurate soft information.Owing to the incremental step pulse programming(ISPP),program errors(PEs)in multi-level cell(MLC)NAND flash memory have different characteristics compared to other types of errors,which is very difficult to obtain such accurate soft information.Therefore,the characteristics of the log-likelihood ratio(LLR)of PEs are investigated first in this paper.Accordingly,a PE-aware statistical method is proposed to determine the usage of PE mitigation schemes.In order to reduce the PE estimating workload of the controller,an adaptive blind clipping(ABC)scheme is proposed subsequently to approximate the PEs contaminated LLR with different decoding trials.Finally,simulation results demonstrate that(1)the proposed PE-aware statistical method is effective in practice,and(2)ABC scheme is able to provide satisfactory bit error rate(BER)and frame error rate(FER)performance in a penalty of negligible increasing of decoding latency.