Monte Carlo Analysis of Yield and Performance of a GaAs Flash ADC

Monte Carlo methods are used to analyze yields and performance of GaAs flash ADCs. Due to the nonuniformity of threshold voltage,the DNL and INL of flash ADC will decrease approximately linearly. And the higher the resolution of ADC is, the faster these key nonlinear parameters decrease. When the nonuniformity increases to some degree,the yields of GaAs flash ADCs will decrease exponentially,and the missing code will increase more quickly for the higher resolution ADCs. So,GaAs HBT and HEMT with technology of etching stop will be widely used in high speed and high resolution ADCs.

一种基于时间域的4倍插值高能效Flash ADC

采用65 nm CMOS工艺,基于时间域4倍插值技术,设计了一款6位3.4 GS/s Flash ADC。该插值技术可以将N位Flash ADC的比较器数量从传统的2^(N)-1减少到2^(N-2)。与传统插值技术不同,该技术利用简单的SR锁存器有效地实现了4倍插值因子,而无需额外的时钟和校准硬件开销,在插值阶段只需要校准2^(N-2)个比较器的失调电压。在不同的工艺角、电源电压和温度(PVT)下,SR锁存器中的失调电压不超过±0.5 LSB。该ADC的采样频率达到3.4 GS/s,其在Nyquist输入时的ENOB达到5.4位,在1V电源下消耗12.6 mW的功耗,其Walden FoM值为89 fJ/(conv·step)。

A Histogram-Based Static-Error Correction Technique for Flash ADCs

High-speed, high-accuracy data converters are attractive for use in most RF applications. Such converters allow direct conversion to occur between the digital baseband and the antenna. However, high speed and high accuracy make the analog components in a converter more complex, and this complexity causes more power to be dissipated than if a traditional approach were taken. A static calibration technique for flash analog-to-digital converters （ADCs） is discussed in this paper. The calibration is based onhistogram test methods, and equivalent errors in the flash ADC comparators are estimated in the digital domain without any significant changes being made to the ADC comparators. In the trimming process, reference voltages are adjusted to compensate for static errors. Behavioral-level simulations of a moderate-resolution 8-bit flash ADC show that, for typical errors, ADC performance is considerably improved by the proposed technique. As a result of calibration, the differential no.nlinearities （DNLs） are reduced on average from 4 LSB to 0.5 LSB, and the integral nonlinearities （INLs） are reduced on average from 4.2 LSB to 0.35 LSB. Implementation issues for this proposed technique are discussed in our subsequent paper, “A Histogram-Based Static-Error Correction Technique for Flash ADCs： Implementation Aspects. ”

A Histogram-Based Static Error Correction Technique for Flash ADCs: Implementation

In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters （ADCs）. In [1], we theoretically describ the calibration technique and perform a behaviorallevel simulation to test its functionality [1]. In this work, we discuss some issues in transistorlevel implementation. The predominant factors that contribute to static errors such as reference generator mismatch and trackandhold （T/H） gain error can be treated as inputreferred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistorlevel implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.

Novel Threshold-Based Standard-Cell Flash ADC

This paper introduces a novel standard-cell flash architecture for implementing analog-to-digital converters (ADC). The proposed ADC consists of several CMOS inverters all having their inputs connected to a common input node. The out-put of the ADC is a thermometer code generated by the inverter outputs. Depending on the relationship between the input signal and a given inverter’s threshold voltage, the output will either be ‘0’ or ‘1’. By having many inverters with different threshold voltages, it is possible to create a 3-bit flash ADC. Even though the system is inherently non-linear, mathematical optimization has been done in order to improve its linearity. The proposed circuit dissipates 6.7 mW and uses in total 672 transistors of PMOS and NMOS types. This ADC is designed and simulated using TSMC’s 0.18 μm CMOS and results show that the proposed circuit works as expected even in presence of process variations.

The Design and Optimization of a Neutron Time-of-Flight Spectrometer with Double Scintillators for Neutron Diagnostics on EAST

Neutron energy spectrometry diagnosis plays an important role in magnetic con- finement fusion. A new neutron time-of-flight （TOF） spectrometer with double scintillators is designed and optimized for the EAST toknmak. A set of optimM parameters is obtained by Monte Carlo simulation, based on the GEANT4 and ROOT codes. The electronic setup of the measurement system is designed. The count rate capability is increased by introducing a flash ADC. The designed spectrometer with high resolution and efficiency is capable of being applied to fusion neutron diagnostics. Applications in mixed-energy and continuous energy neutron fields can also be considered.

Novel Design of Low-power Multiplex Differential Voltage Comparators

A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of the comparators are redundant in some instances, and thus can be turned off. By selecting and switching the current routes, several effective differential pairs are biased by a single tail current stage-by-stage and the redundant comparators are turned off by cutting their tail currents. As a result, the quiescent current and power consumption are greatly decreased. The switching of current is achieved by the input differential pair transistors themselves and hence no extra switches are required. When a MDVC is used in a flash analog-to-digital converter(ADC), its current dissipation is much lower than that of the conventional comparators. This architecture can also be used in window-comparators, maximum or minimum comparators, and comparators for logical operations. The power dissipation in all these cases could be reduced significantly.

Enhanced Offset Averaging Technique for Flash ADC Design

This paper presents a new combined AC/DC-coupled output averaging technique for input amplifier design of flash analog-to-digital converters （ADC）. The new offset averaging design technique takes full advantage of traditional DC-coupled resistance averaging and AC-coupled capacitance averaging techniques to minimize offset-induced ADC nonlinearities. Circuit analysis allows selection of optimum resistance and capacitance averaging factors to achieve maximum offset reduction in ADC designs. The new averaging method is verified in designing a 4 bit 1 Gs/s flash ADC that is implemented in foundry 0.13 μm CMOS technology.

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-UWB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.

Digital post-calibration of a 5-bit 1.25 GS/s flash ADC

We report a high-speed flash analog to digital converter（ADC） linearization technique employing the inverse Volterra model and digital post processing.First,a 1.25 GS/s 5-bit flash ADC is designed using a 0.18μm CMOS,and the signal is quantized by a distributed track-and-hold circuit.Second,based on the Volterra series, a proposed digital post-calibration model is introduced.Then,the model is applied to estimate and compensate the nonlinearity of the high-speed flash ADC.Simulation results indicate that the distortion is reduced effectively. Specifically,the ADC achieves gains of 4.83 effective bits for a 117.1 MHz frequency input and 4.74 effective bits for a Nyquist input at 1.25 GS/s.

Comparison of thermal neutron detection ef f iciency of 6Li scintillation glass and 3He gas proportional tube

We report on a comparison study of the 3He gas proportional tube and the 6Li incorporated scintillation glasses on thermal neutron detection efficiency. Both 3He and 6Li are used commonly for thermal neutron detection because of their high neutron capture absorption coefficient. By using a neutron source 252Cf and a paraffin moderator in an alignment system, we can get a small beam of thermal neutrons. A flash ADC is used to measure the thermal neutron spectrum of each detector, and the detected number of events is determined from the spectrum, then we can calculate the detection efficiency of different detectors. Meanwhile, the experiment has been modeled with GEANT4 to validate the results against the Monte Carlo simulation.