Flip Chip技术在集成电路封装中的应用

阐述从集成电路封装发展现状、Flip Chip技术内涵、Flip Chip技术在集成电路封装中的应用剖析、市场发展展望等多个角度,探讨在集成电路封装中,应用Flip Chip技术的必要性和重要性。

Flip Chip结构的IC信号完整性仿真分析

针对Flip Chip封装型芯片设计过程中存在的传输线阻抗不连续与串扰过大等问题,从层叠设置与板材介质厚度两个角度提出了一种基于阻抗、串扰的仿真分析设计方法,主要涉及两个方面:对于由信号参考平面被分割而造成的阻抗突变问题,通过添加参考平面而使信号具有完整的回流路径,使得传输线的阻抗在平面分割处由167.5Ω降至52.5Ω;对于因布线密度过大而造成的走线之间的串扰系数偏高的问题,通过减小板材的介质厚度使传输线间串扰系数的最大值从17.26%降至14.01%。仿真结果表明,此设计方法有效降低了芯片设计中潜在的信号完整性风险,提高了芯片的可靠性和稳定性。

The Numerical Analysis of Strain Behavior at Solder Joint and Interface of Flip Chip Package

The flip chip package is a kind of advanced electri ca l packages. Due to the requirement of miniaturization, lower weight, higher dens ity and higher performance in the advanced electric package, it is expected that flip chip package will soon be a mainstream technology. The silicon chip is dir ectly connected to printing circuit substrate by SnPb solder joints. Also, the u nderfill, a composite of polymer and silica particles, is filled in the gap betw een the chip and substrate around the solder joints to improve the reliabili ty of solder joints. When flip chip package specimen is tested with thermal cycl ing, the cyclic stress/strain response that exists at the underfill interfaces and solder joints may result in interfacial crack initiation and propagation. Therefore, the chip cracking and the interfacial delamination between underfill and chip corner have been investigated in many studies. Also, most researches h ave focused on the effect of fatigue and creep properties of solder joint induce d by the plastic strain alternation and accumulation. The nuderfill must have lo w viscosity in the liquid state and good adhesion to the interface after solidif ying. Also, the mechanical behavior of such epoxy material has much dependen ce on temperature in its glass transition temperature range that is usually cove red by the temperature range of thermal cycling test. Therefore, the materia l behavior of underfill exists a significant non-linearity and the assumption o f linear elastic can lack for accuracy in numerical analysis. Through numerical analysis, this study had some comparisons about the effect of linear and non -linear properties of underfill on strain behaviors around the interface of fli p chip assembly. Especially, the deformation tendency inside solder bumps could be predicted. Also, it is worthily mentioned that we have pointed out which comp onent of plastic strain, thus, either normal or shear, has dominant influence to the fatigue and creep of solder bump, which have not brought up before. About the numerical analysis to the thermal plastic strain occurs in flip chip i nterconnection during thermal cycling test, a commercial finite element software , namely, ANSYS, was employed to simulate the thermal cycling test obeyed by MIL-STD-883C. The temperatures of thermal cycling ranged from -55 ℃ to 125 ℃ with ramp rate of 36 ℃/min and a dwell time of 25 min at peak temperature. T he schematic drawing of diagonal cross-section of flip chip package composed of FR-4 substrate, silicon chip, underfill and solder bump was shown as Fig.1. Th e numerical model was two-dimensional (2-D) with plane strain assumption and o nly one half of the cross-section was modeled due to geometry symmetry. The dim ensions and boundary conditions of numerical model were shown in Fig.2. The symm etric boundary conditions were applied along the left edge of the model, and the left bottom corner was additional constrained in vertical direction to prevent body motion. The finite element meshes of overall and local numerical model was shown as Fig.3. In this study, two cases of material model were used to describe the material behavior of the underfill: the case1 was linear elastic model that assumed Young’s Modulus (E) and thermal expansion coefficient (CTE) were consta nt during thermal cycling; the case2 was MKIN model (in ANSYS) that had nonlinea r temperature-dependent stress-strain relationship and temperature-dependent CTE. The material model applied to the solder bump was ANAND model (in ANSYS) th at described time-dependent plasticity phenomenon of viscoplastic material. Bot h the FR-4 substrate and silicon chip were assumed as temperature-independent elastic material; moreover, FR-4 substrate is orthotropic while silicon chip is isotropic. From the comparison between numerical results of linear and nonlinear material a ssumption of underfill, (i.e. case1 and case2), the quantities of plastic strain around the interconnection from case1 are higher than that in case2. Thus, the linear

Flip Chip Die-to-Wafer Bonding Review:Gaps to High Volume Manufacturing

Flip chip die-to-wafer bonding faces challenges for industry adoption due to a variety of technical gaps or process integration factors that are not fully developed to high volume manufacturing(HVM)maturity.In this paper,flip-chip and wire bonding are compared,then flip-chip bonding techniques are compared to examine advantages for scaling and speed.Specific recent 3-year trends in flip-chip die-to-wafer bonding are reviewed to address the key gaps and challenges to HVM adoption.Finally,some thoughts on the care needed by the packaging technology for successful HVM introduction are reviewed.

EVOLUTION OF MICROSTRUCTURE OF Sn-Ag-Cu LEAD-FREE FLIP CHIP SOLDER JOINTS DURING AGING PROCESS

Flip chip bonding has become a primary technology that has found application in the chip interconnection process in the electronic manufacturing industry in recent years. The solder joints of the flip chip bonding are small and consist of complicated microstructures such as Sn solution, eutectic mixture, and intermetallic compounds (IMCs), whose mechanical performance is quite different from the original solder bulk. The evolution of microstructure of the flip chip solder joints under thermal aging was analyzed. The results show that with an increase in aging time, coarsening of solder bulk matrix and AuSn4 IMCs occurred within the solder. The IMCs that are formed at the bottom side of the flip chip bond were different from those on the top side during the aging process. (Cu,Ni,Au)6Sn5 were formed at the interfaces of both sides, and large complicated (Au,Ni,Cu)Sn4 IMCs appeared for some time near the bottom interface after aging, but they disappeared again and thus (Cu,Ni,Au)6Sn5 IMC thickness increased considerably. The influence of reflow times during the flip chip bonding (as-bonded condition) on the characteristics of interfacial IMCs was weakened when subjected to the aging process.

Effects of ultrasonic bonding parameters on reliability of flip chip GaN-based light emitting diode

This work applied the ultrasonic bonding to package flip chip GaN-based light emitting diodes (flip chip LEDs) on Si substrates.The effects of ultrasonic bonding parameters on the reliability of flip chip GaN-based LED were investigated.In the sequent aging tests,samples were driven with a constant current of 80 mA for hundreds hours at the room temperature.It was found that the electroluminescence (EL) intensity variation had a large correlation to the ultrasonic power,and then to the bonding temperature and force.A high bonding temperature and ultrasonic power and a proper bonding force improved the EL intensity significantly.It was contributed to a strong atom inter-diffusion forming a stable joint at the bonding interface.The temperature fluctuation in the aging test was the main factor to generate a high inner stress forming delamination at the interface between the chip and Au bump.As a result,delamination had retarded the photons to emit out of the LED packaging and decay its EL intensity.

Ultrasonic power features of wire bonding and thermosonic flip chip bonding in microelectronics packaging

The driving voltage and current signals of piezoceramic transducer (PZT) were measured directly by designing circuits from ultrasonic generator and using a data acquisition software system. The input impedance and power of PZT were investigated by using root mean square (RMS) calculation. The vibration driven by high frequency was tested by laser Doppler vibrometer (PSV-400-M2). And the thermosonic bonding features were observed by scanning electron microscope (JSM-6360LV). The results show that the input power of bonding is lower than that of no load. The input impedance of bonding is greater than that of no load. Nonlinear phase, plastic flow and expansion period, and strengthening bonding process are shown in the impedance and power curves. The ultrasonic power is in direct proportion to the vibration displacement driven by the power, and greater displacements driven by high power (>5 W) result in welding failure phenomena, such as crack, break, and peeling off in wedge bonding. For thermosonic flip chip bonding, the high power decreases position precision of bonding or results in slippage and rotation phenomena of bumps. To improve reliability and precision of thermosonic bonding, the low ultrasonic power (about 1-5 W) should be chosen.

倒装晶片(Flip Chip)装配工艺及其对表面贴装设备的要求

元件的小型化高密度封装形式越来越多,如多模块封装(MCM),系统封装(SiP),倒装晶片(FC)等应用得越来越多。这些技术的出现更加模糊了一级封装与二级装配之间的界线,勿庸置否,随着小型化高密度封装的出现,对高速与高精度装配的要求变得更加关键。相关的组装设备和工艺也更具先进性与高灵活性。由于倒装晶片比BGA或CSP具有更小的外形尺寸,更小的球径和球间距,它对植球工艺,基板技术,材料的兼容性,制造工艺以及检查设备和方法提出了前所未有的挑战。

A Novel Magnetic Bead-based Biosensor Using Flip Chip Bonding Techniques

Based on flip-chip packaging,a novel approach towards integrated magnetic bio-separator was designed.The magnetic field and the force on the bead were simulated and analyzed,leading to the optimization of the fabrication parameters of the micro-magnetic unit.The planar coil as an electromagnet was fabricated through electroplating on a single seed layer. The PDMS microfluidic channel was bonded on the inverse side after Si etching.The results presented in this paper provide a novel design and fabrication to approach a microfluidic bio-separation system with magnetic beads.

Flip-chip芯片关键技术的研究

Flip chip是一种微电子制造表面贴装新工艺,应用于生产还有一些问题未能得到很好的解决。本文通过对组装工艺过程中热应力、封装工艺等关键技术问题的研究,建立了热应力、焊接过程力学模型,为Flip chip的生产进行了一些富有意义的探索。

A novel approach for flip chip inspection based on improved SDELM and vibration signals

This paper proposes a novel nondestructive diagnostic method for flip chips based on an improved semi-supervised deep extreme learning machine(ISDELM)and vibration signals.First,an ultrasonic transducer is used to generate and focus ultrasounds on the surface of the flip chip to excite it,and a laser scanning vibrometer is applied to acquire the chip’s vibration signals.Then,an extreme learning machine-autoencoder(ELM-AE)structure is adopted to extract features from the original vibration signals layer by layer.Finally,the study proposes integrating the ELM with sparsity neighboring reconstruction to diagnose defects based on unlabeled and labeled data.The ISDELM algorithm is applied to experimental vibration data of flip chips and compared with several other algorithms,such as semi-supervised ELM(SS-ELM),deep ELM,stacked autoencoder,convolutional neural network,and ordinary SDELM.The results show that the proposed method is superior to the several currently available algorithms in terms of accuracy and stability.

面积阵列封装——BGA和FlipChip

随着表面安装技术的迅速发展，新的封装技术不断出现，面积阵列封装技术成了现代封装的热门话题。ＢＧＡ和ＦｌｉｐＣｈｉｐ是面积阵列封装的两大类型，它们作为当今大规模集成电路的封装形式，引起了电子组装界的关注，而且逐渐在不同领域得到应用。ＢＧＡ和ＦｌｉｐＣｈｉｐ的出现，适应了表面安装技术的需要，解决了高密度、高性能、多功能及高Ｉ／Ｏ数应用的封装难题，预计随着进一步的发展，ＢＧＡ和ＦｌｉｐＣｈｉｐ技术将成为“最终的封装技术”。本文就ＢＧＡ和ＦｌｉｐＣｈｉｐ的结构、类型、应用及发展等诸多方面进行了阐述。

Reliability of flip-chip bonded RFID die using anisotropic conductive paste hybrid material

A reliability of flip-chip bonded die as a function of anisotropic conductive paste (ACP) hybrid materials, bonding conditions, and antenna pattern materials was investigated during the assembly of radio frequency identification(RFID) inlay. The optimization condition for flip-chip bonding was determined from the behavior of bonding strength. Under the optimized condition, the shear strength for the antenna printed with paste-type Ag ink was larger than that for Cu antenna. Furthermore, an identification distance was varied from the antenna materials. Comparing with the Ag antenna pattern, the as-bonded die on Cu antenna showed a larger distance of identification. However, the long-term reliability of inlay using the Cu antenna was decreased significantly as a function of aging time at room temperature because of the bended shape of Cu antenna formed during the flip-chip bonding process.

倒装焊芯片封装微通孔的一种失效机理及其优化方法

随着晶圆工艺节点的发展,封装集成度越来越高,封装有机基板的线宽和线距逐步减少,微通孔的数量增加,微通孔的孔径减少。球栅阵列(BGA)封装有机基板的微通孔失效一直是影响高性能和高密度芯片封装可靠性的主要问题。针对有机基板微通孔失效的问题,通过温度循环可靠性试验、有限元分析方法、聚焦离子束、扫描电子显微镜以及能谱仪等表征手段,系统研究了-65℃~150℃与-55℃~125℃500次温度循环加载条件下倒装焊的失效模式。结果表明,在-65℃~150℃温度循环条件下,有机基板微通孔由温度循环疲劳应力而产生微通孔分层,仿真表明-65℃~150℃下基板平均等效应力增加约8 MPa;通过改善散热盖结构,等效应力降低了21.4%,且能通过-65℃~150℃500次温度循环的可靠性验证,满足高可靠性的要求。

260 GHz GaN高功率三倍频器设计

基于GaN太赫兹二极管芯片,采用非平衡式电路结构,设计了一款260 GHz三倍频器。采用GaN肖特基二极管芯片提高电路的耐受功率和输出功率;采用“减高+减宽”的输出波导结构抑制二次谐波;采用高低阻抗带线结构设计了倍频器的输入滤波器和输出滤波器。测试结果显示,该三倍频器在261 GHz峰值频率下,实现最大输出功率为69.1 mW,转换效率为3.3%,同时具有较好的谐波抑制特性。

一种基于倒装芯片的超宽带BGA封装差分传输结构

随着高速数字电路和射频微波电路对时钟频率和带宽的要求越来越高,差分传输结构因其优良的噪声抑制和抗干扰性能而受到越来越多的重视。提出了一种基于倒装芯片的超宽带球栅阵列(BGA)封装差分传输结构。整体传输结构包括采用陶瓷材料制作的倒装芯片用基板、BGA封装焊球和印制电路板(PCB)。主要分析了差分垂直传输结构的尺寸参数对阻抗和截止频率的影响,并利用阶梯过孔减小阻抗不连续性。整体结构的传输性能通过矢量网络分析仪测试的散射参数来表征。测试与仿真结果具有较好的一致性,在DC~60 GHz频段,差分传输结构的回波损耗≤-15 dB,插入损耗优于-1 dB,为超宽带倒装芯片的封装设计提供参考。

高精度倒装焊机的光学对位系统

红外焦平面探测器芯片的像元阵列规模不断扩大,像元尺寸不断减小,与读出电路基板的精确互连变得愈加困难,对用于互连工艺核心设备倒装焊机提出了更高的要求。为实现探测器芯片与读出电路基板的精确互连,通过分析倒装焊接工艺的流程,得出芯片与基板的调平和对准是关键环节。介绍了倒装焊机光学对位系统的组成,并对其准直光路系统、显微成像系统、激光测距系统进行了研究。

刚性有机封装基板标准的研制与进展

随着对先进封装需求的快速增加,作为封装载体的封装基板的需求也大幅度增加,而国际和国内的标准化组织暂时都还没有制订出刚性有机封装基板的产品标准,生产厂家、用户对产品的质量要求和检验方法等无法有效统一,容易造成重复认证和质量问题的经济索赔等。要解决这些矛盾,就需要研制用户和生产厂家都能接受的产品标准。本文就刚性有机封装基板标准的研制进行了探讨,并展示了最新的进展。