DESIGN OF nMOS QUATERNARY FLIP-FLOPS AND THEIR APPLICATIONS

By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed. These flip-flops have the capability of two-input presetting and double-rail complementary outputs. It is shown that these flip-flops are effectively suitable to design nMOS quaternary sequential circuits by designing two examples of hexadecimal up-counter and decimal up-counter.

DESIGN OF TERNARY FLIP-FLOPS AND SEQUENTIAL CIRCUITS BASED UPON U_h GATE

According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.

An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies(Invited paper)

Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.

ANALYSIS OF TERNARY SEQUENTIAL CIRCUITS BASED ON TERNARY FLIP-FLOPS

In recent years effort has been made in overcorning an obstacle for multivalued logic to be practically used — the lack of suitable storage elements. Refs. [1—3] proposed the design of master-slave JKL type, T type, D type tri-flops and edge-triggered D type, T

Design of dual-edge triggered flip-flops based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology has been widely considered as an alternative to complementary metal-oxide-semiconductor (CMOS) due to QCA's inherent merits.Many interesting QCA-based logic circuits with smaller feature size,higher operating frequency,and lower power consumption than CMOS have been presented.However,QCA is limited in its sequential circuit design with high performance flip-flops.Based on a brief introduction of QCA and dual-edge triggered (DET) flip-flop,we propose two original QCA-based D and JK DET flip-flops,offering the same data throughput of corresponding single-edge triggered (SET) flip-flops at half the clock pulse frequency.The logic functionality of the two proposed flip-flops is verified with the QCADesigner tool.All the proposed QCA-based DET flip-flops show higher performance than their SET counterparts in terms of data throughput.Furthermore,compared with a previous DET D flip-flop,the number of cells,covered area,and time delay of the proposed DET D flip-flop are reduced by 20.5%,23.5%,and 25%,respectively.By using a lower clock pulse frequency,the proposed DET flip-flops are promising for constructing QCA sequential circuits and systems with high performance.

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.

多种模式降水预报的稳定性特征研究

预报的稳定性是指对同一时段在不同时间发布的多时效预报结论的一致性,是模式预报质量的一个重要方面,较大的不稳定性会给使用者造成困扰。为深入了解业务常用模式的稳定性,使用相对标准偏差指标计算不同时效预报的降水量波动大小,并改进了Flip-Flop指数(改进后简称FF_(norm)),计算多时效降水量预报变化趋势的翻转程度,衡量预报变化趋势的稳定性,对2种全球模式(ECMWF、NCEP-GFS)、3种区域模式(CMA-MESO、CMA-SH9、HHUPS-ST),在中国6个气候分区中降水预报的稳定性进行对比分析,分为实况有降水和暴雨及以上降水2种情况进行了讨论。结果表明:实况有降水时,相对区域模式来说,全球模式的多时效降水预报的相对标准偏差较小,即模式降水量预报的波动较小;各模式对西南区的西部、东北区的东部以及华南区的南部预报的波动性相对较小,西北区的西部波动性较大。就多时效降水量预报变化趋势而言,2种情况下均为CMA-MESO、NCEP-GFS和ECMWF的稳定性较好,其FF_(norm)指数小于HHUPS-ST和CMA-SH9模式,其中CMA-MESO对西南区、华南部分地区降水量预报变化趋势的稳定性较为突出;CMA-SH9的指数最大,多时效降水量预报变化趋势稳定性较差;各模式对长江中下游地区的FF norm指数相对较大,多时效预报趋势的稳定性较差。有降水时,CMA-MESO随时效临近的降水量预报变化趋势稳定(单调递增、单调递减或不变)的频次最多,其次是NCEP-GFS,2种降水情况下,该2种模式的降水量预报均为随时效临近单调递增次数大于递减次数,且CMA-MESO单调递增特征尤其显著。以上特征能够为模式调试和预报决策提供参考。

On Switching of a Flip-Flop Jet Nozzle with Double Ports by Single-Port Control

This research deals with the oscillation mechanism of a flip-flop jet nozzle with a connecting tube, based on the measurements of pressures and velocities in the connecting tube and inside the nozzle. The measurements are carried out varying: 1) the inside diameter d of the connecting tube;2) the length L of the connecting tube and 3) the jet velocity VPN from a primary-nozzle exit. We assume that the jet switches when a time integral reaches a certain value. At first, as the time integral, we introduce the accumulated flow work of pressure, namely, the time integral of mass flux through a connecting tube into the jet-reattaching wall from the opposite jet-un-reattaching wall. Under the assumption, the trace of pressure difference between both the ends of the connecting tube is simply modeled on the basis of measurements, and the flow velocity in the connecting tube is computed as incompressible flow. Second, in order to discuss the physics of the accumulated flow work further, we conduct another experiment in single-port control where the inflow from the control port on the jet-reattaching wall is forcibly controlled and the other control port on the opposite jet-un-reattaching wall is sealed, instead of the experiment in regular jet’s oscillation using the ordinary nozzle with two control ports in connection. As a result, it is found that the accumulated flow work is adequate to determine the dominant jet- oscillation frequency. In the experiment in single-port control, the accumulated flow work of the inflow until the jet’s switching well agrees with that in regular jet’s oscillation using the ordinary nozzle.

RESEARCH INTO TERNARY EDGE-TRIGGERED JKL FLIP-FLOP

The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.

Flip-Flop Flow Control inside Streamwise Diverging Diamond-Shaped Cylinder Bundles with Concavities

The flow visualization work with the aid of PIV and Piezometer deals with flip-flop flow around diamond-shaped cylinder bundle revised with concavities on both bundle walls. It is disclosed that 1) the concavity constructed on both side-walls of a diamond cylinder induces a substantial change in the flow patterns in the exit jet-stream field and jet- stream dispersion, 2) pressure characteristics are quantitatively measured in a diverging-flow region in diamond cylinder bundles with concavityand in its downstream region, and 3) flip-flop flow occurs in the flow passages and its occurrence condition is obtained.

Numerical Simulation of an All Optical Flip-Flop Based on a Nonlinear Distributed Bragg Reflector Laser Structure

A new design for an all optical flip flop is introduced. It is based on a nonlinear Distributed Bragg Reflector (DBR) semiconductor laser structure. The device does not require a holding beam. An optical gain medium confined between 2 Bragg reflectors forms the device. One of the Bragg reflectors is detuned from the other by making its average refractive index slightly higher, and it has a negative nonlinear coefficient that is due to direct absorption at Urbach tail. At low light intensity in the structure, the detuned Bragg reflector does not provide optical feedback to start a laser mode. An optical pulse injected to the structure reduces the detuning of the nonlinear Bragg reflector and a laser mode builds up. The device is reset by detuning the second Bragg reflector optically by an optical pulse that generates electron-hole pairs by direct absorption. A mathematical model of the device is introduced. The model is solved numerically in time domain using a general purpose graphics processing unit (GPGPU) to increase accuracy and to reduce the computation time. The switching dynamics of the device are in nanosecond time scale. The device could be used for all optical data packet switching/routing.

An Improved Design for an All-Optical Flip-Flop Based on a Nonlinear 3-Sections DFB Laser Cavity

A new all optical flip-flop based on a 3-sections nonlinear semiconductor DFB laser structure is proposed and simulated. The operation of the device does not require a holding beam. Electrical current injection into an active layer provides optical gain to the laser mode. The wave-guiding layer consists of a linear grating section centered between 2 detuned nonlinear grating sections. The average refractive index in the nonlinear sections is slightly higher than the refractive index of the middle section. A negative nonlinear refractive index coefficient exists along the nonlinear sections. In the “OFF” state, the DFB structure does not provide enough optical feedback to lase due to the detuned sections. At high light intensity in structure, “ON” state, detuning decreases and the DFB structure allows for a laser mode that sustains the decrease in detuning to exist. The nonlinearity is provided by direct photon absorption at the Urbach tail. Numerical simulations using GPGPU computing show nanoseconds transition times between “OFF” and “ON” states.

Simulations of a Novel All-Optical Flip-Flop Based on a Nonlinear DFB Laser Cavity Using GPGPU Computing

A new all-optical flip-flop based on a nonlinear Distributed feedback (DFB) structure is proposed. The device does not require a holding beam. A nonlinear part of the grating is detuned from the remaining part of the grating and has negative nonlinear coefficient. Optical gain is provided by an injected electrical current into an active layer. In the OFF state, due to the detuned section, no laser light is generated in the device. An injected optical pulse reduces the detuning of the nonlinear section, and the optical feedback provided by the DFB structure generates a laser light in the structure that sustains the change in the detuned section. The device is switched “OFF” by detuning another section of the grating by a Reset pulse. The Reset pulse reduces the refractive index of that section by the generation of electron-hole pairs. The Reset pulse wavelength is adjusted such that the optical gain provided by the active layer at that wavelength is zero. The Reset pulse is prevented from reaching the nonlinear detuned section by introducing an optical absorber in the laser cavity to attenuate the pulse. The device is simulated in time domain using General Purpose Graphics Processing Unit (GPGPU) computing. Set-Reset operations are in nanosecond time scale.

A NEW ASM DESIGN METHOD

A novel ASM one-zero-hot design method based upon ternary flip-flops with binaryconstruction as storage cells is presented.

Influence of Spin-Orbit Force on Nucleon-Nucleon Scattering in the Quark Delocalization Colour Screening Model

The symmetric spin-orbit interactions of one-gluon-exchange and confinement are included in the nucleon-nucleon phase shift calculation in the framework of quark delocalization eolour screening model. The spin-orbit interaction has little influence on D wave phase shift. For the triplet P waves, aPT is in good agreement with the experimental data and 3pLs is attractive but not strong enough, whereas 3 Pc is too strongly repulsive. Our results indicate that the symmetric spin-orbit interaction of one-gluon-exchange and confinement potential cannot give a good description of the triplet P wave phase shifts. More sophisticated considerations, the delocalization depending on the relative orientation between two cluster, might be needed to improve the description of P-wave NN interaction.

The Impact of pH and Air on the Phospholipid Nanostructure Surface

Phospholipids (PLs) in the form of nanostructures are widely employed as a lubricant and antimicrobial agent. The cartilage (AC) surface was characterized using wettability test fresh and depleted AC samples. Cartilage wet surface exposure to air causes increase in surface wettability from 0 to 104 degrees. Effect is explained by flip-flop of the PLs molecules in membrane. The hydrophilic and hydrophobic character of cartilage was determined. Microscopic image of PLs bilayers adsorbed on the surface of pleural tissues and human stomach will be compared with cartilage tissue.

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Now a days,MOS Current Mode Logic(MCML)has emerged as a better alternative to Complementary Metal Oxide Semiconductor(CMOS)logic in digital circuits.Recent works have only traditional logic gates that have issues with information loss.Reversible logic is incorporated with MOS Current Mode Logic(MCML)in this proposed work to solve this problem,which is used for multiplier design,D Flip-Flop(DFF)and register.The minimization of power and area is the main aim of the work.In reversible logic,the count of outputs and inputs is retained as the same value for creating one-to-one mapping.A unique output vector set can be generated for each input vector set and information loss is also prevented.In reversible MCML based multiplier,reversible logic full adder is utilized to minimize the area and power.D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register.The proposed reversible MCML multiplier attains average power of 0.683 mW,Reversible MCML based DFF achieves 0.56μW and Reversible MCML based 8-bit register attains 04.04μW.The result shows that the proposed Reversible MCML based multiplier,Reversible MCML based D flip-flop and ReversibleMCML based register achieves better performance in terms of current,power dissipation,average power and area.

Forced Convection Heat Transfer Coefficient and Pressure Drop of Diamond-Shaped Fin-Array

Forced convection cooling of fins on a high-temperature wall has been used to cool high-power electronic devices. We numerically calculated and experimentally measured the forced convection heat transfer coefficient and pressure drop of a diamond-shaped fin-array with water flow in this study, which had been reported to have a self-induced flip-flop flow phenomenon. Although the flip-flop flow phenomenon occurred in calculations, it was not observed in experiments. The heat transfer and pressure drop of the diamond-shaped fin-array could be estimated with equations for turbulent flow in tubes.

A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock

A new CMOS quaternary D flip-flop is implemented employing a multiple-valuedclock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared withtraditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterizedby improved storage capacity, flexible logic structure and reduced power dissipation.

Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit

The problems existing in the binary logic system and the advantages of multiple-valued logic (MVL) are introduced. A literal circuit with three-track-output structure is created based on resonant tunneling diodes (RTDs) and it has the most basic memory function. A ternary RTD D flip-flop with pre-set and pre-reset functions is also designed, the key module of which is the RTD literal circuit. Two types of output structure of the ternary RTD D flip-flop are optional: one is three-track and the other is single-track; these two structures can be transformed conveniently by merely adding tri-valued RTD NAND, NOR, and inverter units after the three-track output. The design is verified by simulation. Ternary flip-flop consists of an RTD literal circuit and it not only is easy to understand and implement but also provides a solution for the algebraic interface between the multiple-valued logic and the binary logic. The method can also be used for design of other types of multiple-valued RTD flip-flop circuits.