Combined effects of cycling endurance and total ionizing dose on floating gate memory cells

The combined effects of cycling endurance and radiation on floating gate memory cell are investigated in detail,and the obtained results are listed below.(i)The programmed flash cells with a prior appropriate number of program and easing cycling stress exhibit much smaller threshold voltage shift than without those in response to radiation,which is ascribed mainly to the recombination of trapped electrons(introduced by cycling stress)and trapped holes(introduced by irradiation)in the oxide surrounding the floating gate.(ii)The radiation induced transconductance degradation in prior cycled flash cell is more severe than those without cycling stress in the programmed state or erased state.(iii)Radiation is more likely to set up the interface generation in programmed state than in erased state.This paper will be useful in understanding the issues involved in cycling endurance and radiation effects as well as in designing radiation hardened floating gate memory cells.

Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated,in which polysilicon is sandwiched between oxide layers as a floating gate.Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed.The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing（P/E） operations at various P/E voltages are discussed.The simulated results show that present memory exhibits a large memory window of 57.5 V,and a high read current on/off ratio of ≈ 10~3.Compared with the reported experimental results,these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects,which shows great promise in device designing and practical application.

Effects of post-annealed floating gate on the performance of AlGaN/GaN heterostructure field-effect transistors

AlGaN/GaN heterostructure field-effect transistors （HFETs） with different floating gate lengths and floating gates annealed at different temperatures, are fabricated. Using the measured capacitance-voltage curves of the gate Shottky contacts for the AlGaN/GaN HFETs, we find that after floating gate experiences 600℃ rapid thermal annealing, the larger the floating gate length, the larger the two-dimensional electron gas electron density under the gate region is. Based on the measured capacitance-voltage and current-voltage curves, the strain of the AlGaN barrier layer in the gate region is calculated, which proves that the increased electron density originates from the increased strain of the AlGaN barrier layer.

STUDIES ON PROGRAMMING FEATURES AND METHODS OF FLOATING GATE MOSFET AS ANALOG MEMORY FOR SYNAPTIC WEIGHTS IN NEURAL NETWORKS

The features of the floating gate devices as analog memory have been investigatedexperimentally.Programming properties of the devices,compatibility and endurance of program-ming,and programming methods are presented in this paper.The results illustrate that thedevice can be used to store the analog weights for the neural networks,and the method that thestored value is adjusted continuously to approach to a given analog values is a rather practicalmethod for storing weights of neural networks.

A novel enhancement mode AlGaN/GaN high electron mobility transistor with split floating gates

A novel enhancement-mode AlGaN/GaN high electron mobility transistor（HEMT） is proposed and studied.Specifically,several split floating gates（FGs） with negative charges are inserted to the conventional MIS structure.The simulation results revealed that the V_（th） decreases with the increase of polarization sheet charge density and the tunnel dielectric（between FGs and AlGaN） thickness,while it increases with the increase of FGs sheet charge density and blocking dielectric（between FGs and control gate） thickness.In the case of the same gate length,the V_（th） will left shift with decreasing FG length.More interestingly,the split FGs could significantly reduce the device failure probability in comparison with the single large area FG structure.

Designing a Full Adder Circuit Based on Quasi-Floating Gate

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

Organic field-effect transistor floating-gate memory using polysilicon as charge trapping layer

In this study,we present an organic field-effect transistor floating-gate memory using polysilicon(poly-Si)as a charge trapping layer.The memory device is fabricated on a N^+-Si/SiO2 substrate.Poly-Si,polymethylmethacrylate,and pentacene are used as a floating-gate layer,tunneling layer,and active layer,respectively.The device shows bidirectional storage characteristics under the action of programming/erasing(P/E)operation due to the supplied electrons and holes in the channel and the bidirectional charge trapping characteristic of the poly-Si floating-gate.The carrier mobility and switching current ratio(Ion/Ioff ratio)of the device with a tunneling layer thickness of 85 nm are 0.01 cm^2·V^-1·s^-1 and 102,respectively.A large memory window of 9.28 V can be obtained under a P/E voltage of±60 V.

Design,modelling,and simulation of a floating gate transistor with a novel security feature

This study proposes a new generation of floating gate transistors(FGT)with a novel built-in security feature.The new device has applications in guarding the IC chips against the current reverse engineering techniques,including scanning capacitance microscopy(SCM).The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate,even in nano-meter scales.The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate.This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic.Furthermore,this model was verified with a simulation.In addition,the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor.The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated.Finally,the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.

基于FPGA误差可控的浮点运算加速器研究

浮点运算是高性能计算(HPC)领域的基础运算。在大数据与云计算的背景下,高性能计算平台需要处理的数据量与日俱增,而且浮点数的舍入误差在大规模、长时程的运算中会产生累积,因此,在提升浮点运算性能的同时保证计算结果的可靠性非常重要。利用现场可编程门阵列(FPGA)可编程、低功耗、灵活性强的特点,针对含复杂单项运算的浮点多项式设计一种浮点运算加速器。基于无误差变换的思想,通过计算得出舍入误差值,将其补偿到浮点数值上,从而实现误差可控。采用异步并行的方式实现运算加速,并通过构建CPU-FPGA平台最大化地利用计算资源,保证计算任务执行的高效性。数据测试结果表明:在不限制对称性下的数值相对论模拟运算中,该加速器在200 MHz的主频下可达到91.85 MFLOPs的峰值性能;与Intel i76700K CPU运行最大线程数的性能相比,该加速器实现了50.54的加速比,并在该条件下获得了平均53.6%的精确结果百分比以及更低的相对误差,表明其具备较高的可靠性。

具有多晶阻挡层的浮空P区IGBT开关特性研究

为了减少浮空P区IGBT结构的栅极空穴积累,改善结构的电磁干扰(EMI)噪声问题,从而提高结构电磁干扰噪声与开启损耗(Eon)之间的折中关系,研究提出了一种具有多晶硅阻挡层的FD-IGBT结构。新结构在传统结构的浮空P区上方引入一块多晶硅阻挡层,阻挡层接栅极,形成与N型漂移区的电势差。新结构在器件开启过程中,多晶硅阻挡层下方会积累空穴,导致栅极附近积累的空穴数量减少,从而降低浮空P区对栅极的反向充电电流。通过TCAD软件仿真结果表明,相比于传统FD-IGBT,新结构开启瞬态的过冲电流(I_(CE))和过冲电压(V_(GE))的峰值分别下降26.5%和8.6%,且在栅极电阻(R_(g))增加时有更好的电流电压可控性;相同开启损耗下,新结构的dI_(CE)/dt、dV_(CE)/dt和dV_(KA)/dt最大值分别降低26.5%,15.1%和26.1%。

基于FGMOS的电压求和电流传送器及其应用设计

提出了一种基于FGMOS晶体管的电压求和电流传送器的设计。通过对FGMOS晶体管的等效电路分析,得到其框图和等效电路,并设计了其电路结构。为了表明所提电压求和电流传送器的实用性,将提出的电压求和电流传送器用于实现受控振荡器和电压求和放大器;通过SPICE仿真结果表明,基于FGMOS的电压求和电流传送器不仅具有较高的线性特性,而且其电压传递增益和电流传递增益分别可达0.99和0.98,此外还有着很好的频率响应性能、±0.5 V的低电源电压、79.8μW的低功耗和14 kΩ~2.1 MΩ的线性电子可调谐电阻。基于电压求和电流传送器设计的受控振荡器具有稳定的正弦输出,而且振荡频率可以通过偏置电流来控制,设计的电压求和放大器具有高输入电阻和可控的增益。

浮体闸门翻转计算与结构分析

提出将浮体闸门充水过程中的旋转下沉运动拆解为下沉和旋转两个独立运动,通过解析法推导出了传统等截面浮体检修闸门充水过程中旋转中心的计算公式;基于旋转中心的计算公式,分析等截面浮体闸门和变截面浮体闸门的翻转过程,并对其吃水深度、所需配重及稳定性进行对比分析,得出变截面浮体闸门结合门底配重的结构形式在翻转过程中稳定性更高且对水深的要求更低。

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.

Gate-to-body tunneling current model for silicon-on-insulator MOSFETs

A gate-to-body tunneling current model for silicon-on-insulator （SOl） devices is simulated. As verified by the mea- sured data, the model, considering both gate voltage and drain voltage dependence as well as image force-induced barrier low effect, provides a better prediction of the tunneling current and gate-induced floating body effect than the BSIMSOI4 model. A delayed gate-induced floating body effect is also predicted by the model.

Realization of an 850V High Voltage Half Bridge Gate Drive IC with a New NFFP HVI Structure

A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is experimentally realized using a thin epitaxial BCD process. Compared with the MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The high side offset voltage in the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure.

NP-Domino, Ultra-Low-Voltage, High-Speed, Dual-Rail, CMOS NOR Gates

In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.

一种昼夜兼容成像EMCCD图像传感器

本文设计制作了一款阵列规模为1024×1024元、像元尺寸为10μm×10μm的昼夜兼容成像EMCCD(electron multiplying charge coupled device),该器件包含国内首次制作的浮置栅放大器,该放大器电荷转换因子(Charge to voltage factor,CVF)为3.57μV/e^(-),满阱55 ke^(-),能够非破坏性判断信号强度。该功能使得场景中微光照区域的像素可以选择性地路由至倍增通道输出,而强光照区域的像素会路由至非倍增通道输出,有了这种场景内可切换增益特性,两种输出的信号重新组合,实现高动态成像。同时为了实现器件在强光应用场合的抗光晕功能,器件像元区域采用了纵向抗晕设计,抗晕倍数为200倍,基于此类器件制作的相机能够恰当地在暗视场中呈现明亮的图像。

脉冲神经网络中的神经形态器件

随着摩尔定律延续放慢,数据强度任务使得基于冯诺依曼结构的传统计算架构面临挑战,需要激发能够模仿大脑的材料、器件以及系统开发,如神经形态计算。对于直接受大脑启发的脉冲神经网络SNN,实现高密度、高能效的脉冲信息处理,需要高扩展性、低功耗的神经形态器件。文章在生物神经元结构、非监督学习规则以及脉冲神经网络分析基础上,探讨SNN中的突触器件、神经元电路以及与环境接口电路。研究表明:CMOS浮栅存储器件、忆阻器件可作为潜力神经形态器件,充分利用器件的物理特性有助于构建高密度、高能效的神经形态电路。

基于FPGA高速浮点控制算法的设计架构与应用

为满足控制系统对高速处理、高精度运算的需求,提出一种基于现场可编程门阵列(FPGA)的高速浮点控制算法的设计架构。利用System Generator工具设计浮点控制算法并生成其IP核;VHDL编写模/数(A/D)、数/模(D/A)转换芯片的驱动逻辑;而后顶层中按照时序逻辑关系连接各模块;最终在FPGA中实现硬件控制。将算法设计架构应用在快速反射镜的闭环控制中,实验结果表明:单精度浮点格式的PID算法执行时间为2~3个采样周期,整个控制算法最快执行仅需10个时钟周期,闭环控制周期为6.55μs。实验验证了提出的算法设计架构具有可行性;该架构设计的控制器具有高速的处理性能和高精度的控制效果。

重离子辐照引发的25 nm NAND Flash存储器数据位翻转

为研究不同注量下浮栅存储单元位翻转特点及其翻转截面变化,以及重离子入射导致的多单元翻转,以两款25 nm NAND Flash存储器为载体开展了重离子实验研究。实验结果表明,单个重离子在击中存储单元灵敏体积的情况下足以引起位翻转,位翻转比率随着注量累积基本呈线性变化。由于处于编程状态阈值电压分布低压区的存储单元倾向于在相邻或靠近的地址上集中分布,随着注量累积,这类存储单元数量迅速减少,而其他大量存储单元的翻转数增长率变化不明显,因此位翻转截面随注量累积呈下降趋势。重离子导致两款器件出现多单元翻转,多单元翻转呈现单列、双列以及列间隔等结构。利用离子电离径迹模型估算得到离子电离有效径迹半径,可以判定多单元翻转是由于一个离子的电离有效径迹覆盖了多个存储单元。