Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial tr...Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.展开更多
The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Lar...The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.展开更多
This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability o...This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.展开更多
In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage...In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage adder （IVA） with three cells stacked in series, without considering electron emission. By means of these two models, some factors affecting the injection current uni- formity are simulated and analyzed, such as the impedances of adders and loads, cell locations, and feed timing of parallel driving pulses. Simulation results indicate that higher impedances of adder and loads are slightly beneficial to improve injection current uniformity. As the impedances of adder and loads increase from 5 Ω to 30Ω, the asymmetric coefficient of feed currents decreases from 10.3% to 6.6%. The current non-uniformity within the first cell is a little worse than that in other downstream cells. Simulation results also show that the feed timing would greatly affect current waveforms, and consequently cause some distortion in pulse fronts of cell output voltages. For a given driving pulse with duration time of 70-80 ns, the feed timing with a time deviation of less than 20 ns is acceptable for the three-cell IVAs, just causing the rise time of output voltages to increase about 5 ns at most and making the peak voltage decrease by 3.5%.展开更多
An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields...An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.展开更多
Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based tr...Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.展开更多
Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive hi...Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive high voltage rectangular pulses when resistive loads or capacitive loads exist. Beyond the normal pulse adder based on solid-state switches, additional metal- oxide-semiconductor field effect transistors are used in each stage for a faster falling edge. Further, the voltage difference between stages is eliminated by balancing windings. In this paper, we represent our theoretical derivation, software simulations and hardware experiments on magnetic self-balance. The experiments show that the voltage difference between stages is eliminated by balancing windings, which matches the result of simulations with almost identical circuits and parameters.展开更多
Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed an...Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.展开更多
Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circu...Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem are also examined. Differences among these adders are addressed and applications of these adders are suggested.展开更多
Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video...Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal<span> and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, </span><i><span>i.e.</span></i><span>, configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm</span><sup><span style="vertical-align:super;">2</span></sup><span> and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.</span>展开更多
Quantum-dot cellular automaton (QCA) is a novel nanotechnology that provides a very different computation platform than traditional CMOS, in which polarization of electrons indicates the digital information. This pape...Quantum-dot cellular automaton (QCA) is a novel nanotechnology that provides a very different computation platform than traditional CMOS, in which polarization of electrons indicates the digital information. This paper demonstrates designing combinational circuits based on quantum-dot cellular automata (QCA) nanotechnology, which offers a way to implement logic and all interconnections with only one homogeneous layer of cells. In this paper, the authors have proposed a novel design of XOR gate. This model proves designing capabilities of combinational circuits that are compatible with QCA gates within nano-scale. Novel adder circuits such as half adders, full adders, which avoid the fore, mentioned noise paths, crossovers by careful clocking organization, have been proposed. Experiment results show that the performance of proposed designs is more efficient than conventional designs. The modular layouts are verified with the freely available QCA Designer tool.展开更多
Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, w...Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.展开更多
Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models bec...Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.展开更多
文摘Decimal arithmetic circuits are promising to provide a solution for accurate decimal arithmetic operations which are not possible with binary arithmetic circuits.They can be used in banking,commercial and financial transactions,scientific measurements,etc.This article presents the Very Large Scale Integration(VLSI)design of Binary Coded Decimal(BCD)-4221 area-optimized adder architecture using unconventional BCD-4221 representation.Unconventional BCD number representations such as BCD4221 also possess the additional advantage of more effectively representing the 10's complement representation which can be used to accelerate the decimal arithmetic operations.The design uses a binary Carry Lookahead Adder(CLA)along with some other logic blocks which are required to perform internal calculations with BCD-4221 numbers.The design is verified by using Xilinx Vivado 2016.1.Synthesis results have been obtained by Cadence Genus16.1 synthesis tool using 90 nm technology.The performance parameters such as area,power,delay,and area-delay Product(ADP)are compared with earlier reported circuits.Our proposed circuit shows significant area and ADP improvement over existing designs.
文摘The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.
基金supported by the Grant number 600/1792 from the vice presidency of research and technology of Shahid Beheshti University,G.C
文摘This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
基金supported by National Natural Science Foundation of China(No.51307141)partly by the State Key Laboratory of Intense Pulsed Radiation Simulation(Northwest Institute of Nuclear Technology)under Contract SKLIPR 1206
文摘In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage adder （IVA） with three cells stacked in series, without considering electron emission. By means of these two models, some factors affecting the injection current uni- formity are simulated and analyzed, such as the impedances of adders and loads, cell locations, and feed timing of parallel driving pulses. Simulation results indicate that higher impedances of adder and loads are slightly beneficial to improve injection current uniformity. As the impedances of adder and loads increase from 5 Ω to 30Ω, the asymmetric coefficient of feed currents decreases from 10.3% to 6.6%. The current non-uniformity within the first cell is a little worse than that in other downstream cells. Simulation results also show that the feed timing would greatly affect current waveforms, and consequently cause some distortion in pulse fronts of cell output voltages. For a given driving pulse with duration time of 70-80 ns, the feed timing with a time deviation of less than 20 ns is acceptable for the three-cell IVAs, just causing the rise time of output voltages to increase about 5 ns at most and making the peak voltage decrease by 3.5%.
文摘An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.
文摘Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.
文摘Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive high voltage rectangular pulses when resistive loads or capacitive loads exist. Beyond the normal pulse adder based on solid-state switches, additional metal- oxide-semiconductor field effect transistors are used in each stage for a faster falling edge. Further, the voltage difference between stages is eliminated by balancing windings. In this paper, we represent our theoretical derivation, software simulations and hardware experiments on magnetic self-balance. The experiments show that the voltage difference between stages is eliminated by balancing windings, which matches the result of simulations with almost identical circuits and parameters.
文摘Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.
文摘Low power adder circuits, SERF, 10T Ⅰ,10T Ⅱ,10T Ⅲ and a complementary adder (28T) at physical layout level are evaluated. Simulations based on the extracted adder circuit layouts are run to assess how various circuit setups can impact the speed and power consumption. In addition, impacts of output inverters on the circuit performance of modified SERF and 10T adders due to threshold loss problem are also examined. Differences among these adders are addressed and applications of these adders are suggested.
文摘Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal<span> and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, </span><i><span>i.e.</span></i><span>, configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm</span><sup><span style="vertical-align:super;">2</span></sup><span> and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.</span>
文摘Quantum-dot cellular automaton (QCA) is a novel nanotechnology that provides a very different computation platform than traditional CMOS, in which polarization of electrons indicates the digital information. This paper demonstrates designing combinational circuits based on quantum-dot cellular automata (QCA) nanotechnology, which offers a way to implement logic and all interconnections with only one homogeneous layer of cells. In this paper, the authors have proposed a novel design of XOR gate. This model proves designing capabilities of combinational circuits that are compatible with QCA gates within nano-scale. Novel adder circuits such as half adders, full adders, which avoid the fore, mentioned noise paths, crossovers by careful clocking organization, have been proposed. Experiment results show that the performance of proposed designs is more efficient than conventional designs. The modular layouts are verified with the freely available QCA Designer tool.
文摘Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.
文摘Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.
