The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode...The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode structure, the folded-cascode mixer （FCM） has a lower power supply voltage of 1.2 V and realizes the design trade-offs among the high transconductance, high linearity and low noise. The difficulties of realizing the trade-offs between the linearity and noise performance, the linearity and conversion gain, the conversion gain and noise performance are reduced. Fabricated in an radio frequency （RF） 0.18 μm CMOS process, the FCM has an active area of about 200 μm ×150 μm and consumes approximate 3.9 mW. The test results show that the FCM features a conversion gain （Gc） of some 14.5 dB, an input 1 dB compression point （Pin-1dB） of almost -13 dBm and a dual sideband （DSB） noise figure of around 12 dB. The FCM can be applied to the navigation radio receivers and electronic systems for aviation and aerospace or other related fields.展开更多
We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs ...We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency(RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator(LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency(IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power(LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain(VCG) of 9.8 d B, a double sideband noise figure(DSB-NF) of 11.6 d B, and a linearity in terms of input 1 d B compression point(Pin,1d B) of-13 d Bm are measured. The mixer draws a current of 5 m A from a 1.2 V supply dissipating a power of only 6 m W.展开更多
A down-conversion in-phase/quadrature （l/Q） mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter （D-QAF）, in order to realize the final down-conversion stage of...A down-conversion in-phase/quadrature （l/Q） mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter （D-QAF）, in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider tbr the local oscillator （LO） of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency （IF） band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency （RF） band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point （IIP3） ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure （SSB-NF） of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.展开更多
文摘The folded-cascode structure is used to realize the low-voltage low-power consumption mixer, whose performance parameters have big influence on the navigation radio receiver＇s performance. Adopting the folded-cascode structure, the folded-cascode mixer （FCM） has a lower power supply voltage of 1.2 V and realizes the design trade-offs among the high transconductance, high linearity and low noise. The difficulties of realizing the trade-offs between the linearity and noise performance, the linearity and conversion gain, the conversion gain and noise performance are reduced. Fabricated in an radio frequency （RF） 0.18 μm CMOS process, the FCM has an active area of about 200 μm ×150 μm and consumes approximate 3.9 mW. The test results show that the FCM features a conversion gain （Gc） of some 14.5 dB, an input 1 dB compression point （Pin-1dB） of almost -13 dBm and a dual sideband （DSB） noise figure of around 12 dB. The FCM can be applied to the navigation radio receivers and electronic systems for aviation and aerospace or other related fields.
基金Project supported by the National High-Tech R&D Program(863)of China(No.2011AA010200)
文摘We present the design of a folded down-conversion mixer which is incorporated at the final down-conversion stage of a 60 GHz receiver. The mixer employs an ac-coupled current reuse transconductance stage. It performs well under low supply voltages, and is less sensitive to temperature variations and process spread. The mixer operates at an input radio frequency(RF) band ranging from 10.25 to 13.75 GHz, with a fixed local oscillator(LO) frequency of 12 GHz, which down-converts the RF band to an intermediate frequency(IF) band ranging from dc to 1.75 GHz. The mixer is designed in a 65 nm low power(LP) CMOS process with an active chip area of only 0.0179 mm2. At a nominal supply voltage of 1.2 V and an IF of 10 MHz, a maximum voltage conversion gain(VCG) of 9.8 d B, a double sideband noise figure(DSB-NF) of 11.6 d B, and a linearity in terms of input 1 d B compression point(Pin,1d B) of-13 d Bm are measured. The mixer draws a current of 5 m A from a 1.2 V supply dissipating a power of only 6 m W.
基金Project supported by the National High Technology Research and Development Program of China(No.2011AA010200)
文摘A down-conversion in-phase/quadrature （l/Q） mixer employing a folded-type topology, integrated with a passive differential quadrature all-pass filter （D-QAF）, in order to realize the final down-conversion stage of a 60 GHz receiver architecture is presented in this work. Instead of employing conventional quadrature generation techniques such as a polyphase filter or a frequency divider tbr the local oscillator （LO） of the mixer, a passive D-QAF structure is employed. Fabricated in a 65 nm CMOS process, the mixer exhibits a voltage gain of 7-8 dB in an intermediate frequency （IF） band ranging from 10 MHz-1.75 GHz. A fixed LO frequency of 12 GHz is used to down-convert a radio frequency （RF） band of 10.25-13.75 GHz. The mixer displays a third order input referred intercept point （IIP3） ranging from -8.75 to -7.37 dBm for a fixed IF frequency of 10 MHz and a minimum single-sideband noise figure （SSB-NF） of 11.3 dB. The mixer draws a current of 6 mA from a 1.2 V supply voltage dissipating a power of 7.2 mW.
