本文介绍一种新颖的'多米诺骨牌'电路。该电路共设三路,其中 A 路原理如附图所示。B和 C 路电路图同 A 路一样。该电路利用十进制计数/译码器 CD4017(IC2、IC3)的十个输出端依次出现高电平,驱动发光二极管 LED 依次点亮,形成移...本文介绍一种新颖的'多米诺骨牌'电路。该电路共设三路,其中 A 路原理如附图所示。B和 C 路电路图同 A 路一样。该电路利用十进制计数/译码器 CD4017(IC2、IC3)的十个输出端依次出现高电平,驱动发光二极管 LED 依次点亮,形成移动的光亮点,来模拟多米诺骨牌的推倒过程,这是一件非常有趣的事情,A、B、C 三路的每一排均由三只 LED 并联组成,用来代替骨牌的每一块,每一路有99排,则 A 路有297只 LED 组成,A、B、C 三路共有891只 LED 组成。所用 LED 越多,推倒过程越有创意,效果越好。A 电路工作原理是:当接通电源时,由LM555(IC1)组成的脉冲振荡器起振,其第③脚输出时钟脉冲 CP 送至 IC2第(14)脚,Y0～Y9依次输出高电平,因这时 IC3第③脚输出高电平,经CD4069(IC4、IC5)的 IC4a 反相后输出低电平,故 X0轴的 VD1～VD10依次发光,当第十只 LED(XD10)点亮后,IC2计数器重新计数。当展开更多
Considering the effect of temperature and process variations, the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-6...Considering the effect of temperature and process variations, the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual threshold voltage （V1） footed domino circuits. HSPICE simulations based on 65nm and 45nm BSIM4 models show that the proposed CLIL state （the clock signal and inputs are all low） is the optimal state to reduce the leakage current of the high fan-in footed domino circuits at high temperature and almost all footed domino circuits at room temperature, as compared to the conventional CHIL state （the clock signal is high and inputs are all low） and the CHIH state （the clock signal and inputs are all high）. Further, the influence of the process variations on the leakage current characteristics of the dual V1 footed domino circuits is evaluated. At last, temperature and process variation aware new low leakage current setup guidelines are provided.展开更多
文摘本文介绍一种新颖的'多米诺骨牌'电路。该电路共设三路,其中 A 路原理如附图所示。B和 C 路电路图同 A 路一样。该电路利用十进制计数/译码器 CD4017(IC2、IC3)的十个输出端依次出现高电平,驱动发光二极管 LED 依次点亮,形成移动的光亮点,来模拟多米诺骨牌的推倒过程,这是一件非常有趣的事情,A、B、C 三路的每一排均由三只 LED 并联组成,用来代替骨牌的每一块,每一路有99排,则 A 路有297只 LED 组成,A、B、C 三路共有891只 LED 组成。所用 LED 越多,推倒过程越有创意,效果越好。A 电路工作原理是:当接通电源时,由LM555(IC1)组成的脉冲振荡器起振,其第③脚输出时钟脉冲 CP 送至 IC2第(14)脚,Y0～Y9依次输出高电平,因这时 IC3第③脚输出高电平,经CD4069(IC4、IC5)的 IC4a 反相后输出低电平,故 X0轴的 VD1～VD10依次发光,当第十只 LED(XD10)点亮后,IC2计数器重新计数。当
基金supported by the2008Science and Research Foundation of Hebei Education Depart ment(No.2008308)~~
文摘Considering the effect of temperature and process variations, the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual threshold voltage （V1） footed domino circuits. HSPICE simulations based on 65nm and 45nm BSIM4 models show that the proposed CLIL state （the clock signal and inputs are all low） is the optimal state to reduce the leakage current of the high fan-in footed domino circuits at high temperature and almost all footed domino circuits at room temperature, as compared to the conventional CHIL state （the clock signal is high and inputs are all low） and the CHIH state （the clock signal and inputs are all high）. Further, the influence of the process variations on the leakage current characteristics of the dual V1 footed domino circuits is evaluated. At last, temperature and process variation aware new low leakage current setup guidelines are provided.
