Fuzzy Based Interleaved Step-up Converter for Electric Vehicle

This work focuses on the fuzzy controller for the proposed three-phase interleaved Step-up converter(ISC).The fuzzy controller for the proposed ISC converters for electric vehicles has been discussed in detail.The proposed ISC direct current(DC-DC)converter could also be used in automobiles,satellites,industries,and propulsion.To enhance voltage gain,the proposed ISC Converter combines boost converter and interleaved converter(IC).This design also reduces the number of switches.As a result,ISC converter switching losses are reduced.The proposed ISC Converter topology can produce a 143 V output voltage and 1 kW of power.Due to the high voltage gain of this converter design,it is suitable for medium and high-power systems.The proposed ISC Converter topology is simulated in MATLAB/Simulink.The simulated output displays a high output voltage.But the output voltage contains maximum ripples.Fuzzy proposes an ISC Converter which makes closed loop responsiveness and reduces the output voltage ripple.The proposed ISC converter has the lowest ripple output voltage,which is less than 2%,because the duty cycle is regulated using the fuzzy logic controller.It offers high voltage gain,minimal ripple,and low switching loss.The performance of the proposed converter is compared to that of the fuzzy and Pro-portional Integral(PI)controllers implemented in MATLAB.

Improved Interleaved Single-Ended Primary Inductor-Converter forSingle-Phase Grid-Connected System

The generation of electricity based on renewable energy sources,parti-cularly Photovoltaic(PV)system has been greatly increased and it is simply insti-gated for both domestic and commercial uses.The power generated from the PV system is erratic and hence there is a need for an efficient converter to perform the extraction of maximum power.An improved interleaved Single-ended Primary Inductor-Converter(SEPIC)converter is employed in proposed work to extricate most of power from renewable source.This proposed converter minimizes ripples,reduces electromagnetic interference due tofilter elements and the contin-uous input current improves the power output of PV panel.A Crow Search Algo-rithm(CSA)based Proportional Integral(PI)controller is utilized for controlling the converter switches effectively by optimizing the parameters of PI controller.The optimized PI controller reduces ripples present in Direct Current(DC)vol-tage,maintains constant voltage at proposed converter output and reduces over-shoots with minimum settling and rise time.This voltage is given to single phase grid via 1�Voltage Source Inverter(VSI).The command pulses of 1�VSI are produced by simple PI controller.The response of the proposed converter is thus improved with less input current.After implementing CSA based PI the efficiency of proposed converter obtained is 96%and the Total Harmonic Distor-tion(THD)is found to be 2:4%.The dynamics and closed loop operation is designed and modeled using MATLAB Simulink tool and its behavior is performed.

Interleaved-Connected Split Planar Resonant Inductor Design in 1 kV SiC LLC Converters

Design method of split planar resonant inductor in 1 kV SiC logical link control(LLC)converter is proposed,which ensures the converter power density of 93.59 W/in^3 and peak efficiency of 95.73%.Split resonant inductor helps to provide symmetrical resonant current by symmetrical impedance,and improves the distortion of resonant current,which ensures the efficiency of the whole converter.An interleaved winding connecting scheme improves the power density of the planar magnets,which contributes to power density improvement.Design method and calculation process of such split planar resonant inductor are provided.To verify the feasibility of the proposed design method,a 1 kV/48 V 6.6 kW,210 k Hz SiC LLC prototype was built,and the experimental results are given.

Research on Parallel Interleaved Inverters with Discontinuous Space-Vector Modulation

Parallel converter can significantly increase the capacity of the converter and improve the power quality of AC side, but the circulation which can lead to high switching loss and even damage the devices will easily exist in the direct parallel converters. In this paper, the average model of parallel interleaved inverters system to analyze the circulation current is shown, and the cross current is relevant to DC-bus voltage and the overlap time of zero vectors in the switching period. Based on this observation, a discontinuous space vector modulation without using zero vectors (000) is eliminate and suppress the zero-sequence current to entire system. Finally, the effectiveness of modulation strategy is verified by the simulations in this paper.

High Power Interleaved Boost Converter for Photovoltaic Applications

Interfacing DC sources to load/power grid requires DC converters that produce minimum level of current ripples. This is to limit the losses and hence increase the life span of these sources. This article proposes a simple inter-leaved boost converter that interfaces PhotoVoltaic (PV) module into a common DC-link. The article also addresses the faulty mode operation of the proposed circuit while advising the appropriate remedy actions. A MATLAB and Simulink dynamic platform are used to simulate the transient performance of the proposed converter. The results revealed the effectiveness and the viability of the proposed converter in reducing the ripples in the PV current without employing bulky input inductors or increasing the switching frequency.

Complexity Reduced MIMO Interleaved SC-FDMA Receiver with Iterative Detection

In this paper, we propose the receiver structure for Multiple Input Multiple Output (MIMO) Interleaved Single Carrier-Frequency Division Multiple Access (SC-FDMA) where the Frequency Domain Equalization (FDE) is firstly done for obtaining the tentative decision results and secondly using them the Inter-Symbol Interference (ISI) is cancelled by ISI canceller and then the Maximum Likelihood Detection (MLD) is used for separating the spatially multiplexed signals. Furthermore the output from MLD is fed back to ISI canceller repeatedly. In order to reduce the complexity, we replace the MLD by QR Decomposition with M-Algorithm (QRD-M) or Sphere Decoding (SD). Moreover, we add the soft output function to SD using Repeated Tree Search (RTS) algorithm to generate soft replica for ISI cancellation. We also refer to the Single Tree Search (STS) algorithm to further reduce the complexity of RTS. By examining the BER characteristics and the complexity reduction through computer simulations, we have verified the effectiveness of proposed receiver structure.

Identification of Typical Rice Diseases Based on Interleaved Attention Neural Network

Taking Jiuhong Modern Agriculture Demonstration Park of Heilongjiang Province as the base for rice disease image acquisition,a total of 841 images of the four different diseases,including rice blast,stripe leaf blight,red blight and bacterial brown spot,were obtained.In this study,an interleaved attention neural network(IANN)was proposed to realize the recognition of rice disease images and an interleaved group convolutions(IGC)network was introduced to reduce the number of convolutional parameters,which realized the information interaction between channels.Based on the convolutional block attention module(CBAM),attention was paid to the features of results of the primary group convolution in the cross-group convolution to improve the classification performance of the deep learning model.The results showed that the classification accuracy of IANN was 96.14%,which was 4.72%higher than that of the classical convolutional neural network(CNN).This study showed a new idea for the efficient training of neural networks in the case of small samples and provided a reference for the image recognition and diagnosis of rice and other crop diseases.

Adaptive blind gain correction of time-interleaved ADCs forwide-band communication applications

High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality.Time-interleaved A/D converter(TI-ADC)is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management.However,practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations.In this paper,a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC,and it is verified through simulations on a two-channel TI-ADC.In proposed method,gain mismatch error is estimated and corrected in an adaptive scheme.Proposed compensated TI-ADC architecture is structurally very simple and hence suitable for realization in integrated circuits.Besides,proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI-ADC.

SPLIT-ADC BASED DIGITAL BACKGROUND CALIBRATION FOR TIME-INTERLEAVED ADC

A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.

Multiple-Symbol Interleaved RS Codes and Two-Pass Decoding Algorithm

For communication systems with heavy burst noise, an optimal Forward Error Correction(FEC) scheme is expected to have a large burst error correction capability while simultaneously owning moderate random error correction capability. This letter presents a new FEC scheme based on multiple-symbol interleaved Reed-Solomon codes and an associated two-pass decoding algorithm. It is shown that the proposed multi-symbol interleaved Reed-Solomon scheme can achieve nearly twice as much as the burst error correction capability of conventional single-symbol interleaved Reed-Solomon codes with the same code length and code rate.

Design and Experimentation of FPGA-Based Soft-Switched Interleaved Boost Converter for Telecommunication System

This paper proposes the design and experimentation of digital control of soft-switched interleaved boost converter using FPGA for Telecommunication System. The switching devices in the proposed converter are turned on and off with Zero Voltage Switching (ZVS) and Zero Current Switching (ZCS) respectively. The circuit is operated in Continuous Conduction Mode (CCM) with various load ranges having duty cycle of more than 50%. The proposed converter is studied by developing the simulation module in MATLAB/SIMULINK. A PI controller is designed and implemented in FPGA to obtain a regulated DC output for line and load variations. Simulation and experimentation results are verified with a prototype development of the proposed converter. The results indicate that the converter performance is enhanced with closed loop control.

Achievable secrecy rate of bit-interleaved coded modulation schemes

We study the impact of various modulation mapping strategies and signal constellation shapes on the se- crecy rates achievable with bit-interleaved coded modulation （BICM） schemes. Transmission over an ergodic Rayleigh fading channel is assumed throughout this work. Various constellations and mapping techniques are considered in this work to maximize the capacity difference between the main channel and the eavesdropper channel, rather than to opti- mize the capacity of both channels. We show that in terms of achievable secrecy rate, Gray and Quasi-Gray mappings only perform Well at low SNR but outperformed by other mapping techniques when SNR increases. The proper design of signal mapping can significantly enhance the achievable secrecy rate in BICM schemes. It is indicated that the key parameter to the secrecy rate of a BICM system is the distance spectrum of Euclidean distances for mappings.

A Timing Skew Calibration Scheme in Time-Interleaved ADC

This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.

Improved time-interleaved error feedback delta sigma modulator for digital transmitter application

Time-interleaved structure can promote the equivalent processing speed of a digital signal processing system. An improved time-interleaved error feedback delta sigma modulator( TI-EF-DSM)for digital transmitter application is presented in this paper. Two TI-EF-DSMs are compared,one is a conventional directly implemented and the other is the improved. The processing speed of the proposed two-channel improved time-interleaved error feedback delta sigma modulator( ITI-EF-DSM) is higher than the conventional directly implemented TI-EF-DSM for shortened critical path. A digital transmitter based on the ITI-EF-DSM is implemented on field progrmmable gate array( FPGA). The long term evolution( LTE) signals with different bandwidths of 5 MHz,10 MHz and 20 MHz are used as the signal source to evaluate the transmitter. The achieved SNR is 41 dB for the 20 MHz LTE signal with the processing clock of only 184 MHz.

A NEW LABELING SEARCH ALGORITHM FOR BIT-INTERLEAVED CODED MODULATION WITH ITERATIVE DECODING

Bit-Interleaved Coded Modulation with Iterative Decoding (BICM-ID) is a bandwidth ef- ficient transmission, where the bit error rate is reduced through the iterative information exchange between the inner demapper and the outer decoder. The choice of the symbol mapping is the crucial design parameter. This paper indicates that the Harmonic Mean of the Minimum Squared Euclidean (HMMSE) distance is the best criterion for the mapping design. Based on the design criterion of the HMMSE distance, a new search algorithm to find the optimized labeling maps for BICM-ID system is proposed. Numerical results and performance comparison show that the new labeling search method has a low complexity and outperforms other labeling schemes using other design criterion in BICM-ID system, therefore it is an optimized labeling method.

两类具有低自相关和大线性复杂度的4p周期二元序列

具有良好自相关性质和大线性复杂度的二元序列设计对于通信系统和流密码的各种应用非常重要.本文从Hall六次剩余序列和它们的修改版本中选取4条合适的序列作为基序列,利用交织技术构造了两类周期为4p的二元序列,并且完全确定了这两类序列的自相关和线性复杂度.研究结果表明这两类序列既具有低自相关性质又具有非常大的线性复杂度.

一种交叉倍压型高增益DC/DC变换器

针对光伏发电、燃料电池发电等领域对高增益直流变换器的需求,以两相交错并联升压变换器为研究对象,由2个含有电感的倍压单元组合设计出实现电压提升的交叉倍压结构,据此提出了一种新颖的交叉倍压型高增益DC/DC变换器。该变换器可实现(3n+4)/(1-d)倍的高电压增益(1∶n为耦合电感匝数比,d为变换器占空比),且具有电路器件的低电压应力特性。对于漏感引起的开关管电压尖峰问题,引入了钳位电容构成释放漏感能量通道,同时提升了输出电压。介绍了新型交叉倍压型高增益变换器的拓扑结构,分析了变换器各模态的工作过程,推导了电压增益、输入电流纹波及各器件电压应力等稳态特性,并搭建样机进行实验研究,验证了该直流变换技术方案的可行性和先进性。

层联衬经斜纹机织预制体细观结构几何建模

为分析层联衬经斜纹机织预制体的细观结构,通过X射线显微镜(Micro-CT)观测复合材料中的纤维,基于Micro-CT观测的纤维横截面形状和空间走向,提出矩形衬经纱横截面、矩形接结经纱横截面、凸透镜形纬纱横截面、直线型衬经纱路径、直线型纬纱路径和抛物线形接结经纱路径等假设,推导了纤维预制体厚度和纤维体积含量与纤维参数之间的关系,建立了预制体细观结构模型,通过纤维宽度和厚度计算纱线横截面变异系数、预制体厚度和纤维体积含量。为验证模型的准确性,以芳纶纤维和超高分子质量聚乙烯纤维为原材料制备了2种相同结构、不同纤维的层联衬经斜纹机织复合材料,并与提出的预制体模型对比分析。结果表明:理论值与实测值在合理误差范围之内,预制体厚度误差小于1.5%,预制体纤维体积含量误差小于1.5%。

基于帧交错的LDPC译码器流水结构设计

低密度奇偶校验码(LDPC)的译码器通常采用基于节点置信度更新迭代的算法,这种算法可以并行实现,具有非常高的吞吐量。在此提出了一种具有高硬件利用效率(HUE)的帧交错译码结构,并提供了一种用于层内节点重排序的动态规划方法,解决内存访问冲突问题。与现有的结构相比,该结构可以实现更高的硬件利用效率。