When applying Grover＇s algorithm to an unordered database, the probabifity of obtaining correct results usually decreases as the quantity of target increases. A four-phase improvement of Grover＇s algorithm is propos...When applying Grover＇s algorithm to an unordered database, the probabifity of obtaining correct results usually decreases as the quantity of target increases. A four-phase improvement of Grover＇s algorithm is proposed to fix the deficiency, and the unitary and the phase-matching condition are also proposed. With this improved scheme, when the proportion of target is over 1/3, the probability of obtaining correct results is greater than 97.82% with only one iteration using two phases. When the computational complexity is O（ √M/N）, the algorithm can succeed with a probability no less than 99.63%.展开更多
The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor netwo...The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.展开更多
基金Supported by the National Basic Research Program of China under Grant No 2013CB338002the National Natural Science Foundation of China under Grant No 11504430
文摘When applying Grover＇s algorithm to an unordered database, the probabifity of obtaining correct results usually decreases as the quantity of target increases. A four-phase improvement of Grover＇s algorithm is proposed to fix the deficiency, and the unitary and the phase-matching condition are also proposed. With this improved scheme, when the proportion of target is over 1/3, the probability of obtaining correct results is greater than 97.82% with only one iteration using two phases. When the computational complexity is O（ √M/N）, the algorithm can succeed with a probability no less than 99.63%.
基金the Hi-Tech Research and Development Program of China（2006AA01Z226）the Scientific Research Foundation of Huazhong University of Science and Technology（2006Z001B)the Natural Science Foundation of Hubei（2006ABA080）.
文摘The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks （WSN）. The design challenges for an efficient WSN mainly lie in two issues： power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte （S-box） transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, l） The composite field arithmetic in GF（（2^4））2 was used to implement the compact datapath circuit; 2） A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit （ASIC） on 0.25 μm complementary mental oxide semiconductor （CMOS） process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property （IP） core for the wireless sensor node chips.
