A New Type of Power Clock for DSCRL Adiabatic Circuit

An asymmetry power clock,4 phase power clock supplying the power to the DSCRL(dual swing charge recovery logic) adiabatic circuit is presented.It is much simpler than the 6 phase power clock,symmetry power clock,used in the DSCRL adiabatic circuit.Although the 4 phase power clock is simpler,the DSCRL adiabatic circuit still shows good performance and high efficiency of energy transfer and recovery.This conclusion has been proved by the result of the HSPICE simulation using the 0 6μm CMOS technology.

Energy Recovery Threshold Logic and Power Clock Generation Circuits

Energy recovery threshold logic (ERTL) is proposed,which combines threshold logic with adiabatic approach.ERTL achieves low energy as well as low gate complexity.A high efficiency power clock generator is also proposed,which can adjust duty cycle of MOS switch in power clock generator depending on logic complexity and operating frequency to achieve optimum energy efficiency.Closed-form results are derived,which facilitate efficiency-optimized design of the power clock generator.An ERTL PLA and a conventional PLA are designed and simulated on 0.35μm process.The energy efficiency of the proposed power clock generator can reach 77%～85% operating between 20～100MHz.Simulation results indicate that ERTL is a low energy logic.Including power loss of power clock circuits,ERTL PLA still shows 65%～77% power savings compared to conventional PLA.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

SYNCHRONOUS DERIVED CLOCK AND SYNTHESIS OF LOW POWER SEQUENTIAL CIRCUITS

Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.

2.5Gb/s Monolithic IC of Clock Recovery,Data Decision,and 1∶4 Demultiplexer

A high integrated monolithic IC, with functions of clock recovery, data decision, and 1 ： 4 demultiplexer,is implemented in 0.25μm CMOS process for 2.5Gb/s fiber-optic communications. The recovered and frequency divided 625MHz clock has a phase noise of -106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data （2^31-1）. The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data. The 0.97mm× 0.97mm IC consumes 550mW under a single 3.3V power supply （not including output buffers）.

同步电路设计中CLOCK SKEW的分析

Clock skew是数字集成电路设计中一个重要的因素。本文比较了在同步电路设计中 0 clock skew和非 0clock skew时钟分布对电路性能的影响 ,分析了通过调整时钟树中 CL OCK SKEW来改善电路性能的方法 ,从而说明非 0 clock skew时钟分布是如何提高同步电路运行的最大时钟频率的。

FPGA-based high resolution DPWM control circuit

Two improved structures of high resolution digital pulse width modulator(DPWM) control circuit are proposed. Embedded digital clock manager(DCM) blocks and digital programmable delay circuits are employed as the basic resources to construct the field-programmable gate array(FPGA)-based DPWM implementations. Detailed schemes are illustrated and the circuits have been successfully implemented on the Artix-7 FPGA device developed by Xilinx. Experimental results show that when the basic clock operates at the frequency of 200 MHz, the resolutions of the two approaches can reach 625 ps and 500 ps, respectively. Besides,the presented schemes possess other merits including flexible resolution, strong versatility and relatively good stability.

A UNIFIED THEORY FOR DESIGNING ANDANALYZING BOTH SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.

Design of Digital Circuit Experiment Course Based on FPGA

With the development of integrated circuit, the content of digital circuit experiment course is constantly updated. In order to keep up with the development trend of the Times and make students’ professional knowledge meet the needs of the industry, the school adopts the FPGA experimental platform to carry out teaching reform from the two aspects of platform and experiment, and carry out reasonable experimental planning to enrich the experimental content. In this paper, the traditional knowledge points of logic algebra, trigger, timer, counter, decoder and digital tube are organically combined, and the digital clock system is designed and realized. The practice shows that the combination of modern design method and traditional digital circuit teaching method can play a good teaching effect. In this way, students can also fully learn, understand and skillfully use the new technology in the experiment, and in the process of building a comprehensive understanding of digital circuits.

A NEW APPROACH TO PROGRAMMABLE LOGIC ARRAY FOR SINGLE-CLOCK CMOS

Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit-low power dissipation and compact structure, this approach also provides high-speed operation.

Design and implementation of control system for superconducting RSFQ circuit

The superconducting rapid single flux quantum(RSFQ)integrated circuit is a promising solu-tion for overcoming speed and power bottlenecks in high-performance computing systems in the post-Moore era.This paper presents an architecture designed to improve the speed and power limitations of high-performance computing systems using superconducting technology.Since superconducting microprocessors,which operate at cryogenic temperatures,require support from semiconductor cir-cuits,the proposed design utilizes the von Neumann architecture with a superconducting RSFQ mi-croprocessor,cryogenic semiconductor memory,a room temperature field programmable gate array(FPGA)controller,and a host computer for input/output.Additionally,the paper introduces two key circuit designs:a start/stop controllable superconducting clock generator and an asynchronous communication interface between the RSFQ and semiconductor chips used to implement the control system.Experimental results demonstrate that the proposed design is feasible and effective,provi-ding valuable insights for future superconducting computer systems.

Design and Analysing the Various Parameters of CMOS Circuit’s under Bi-Triggering Method Using Cadence Tools

Reducing the power and energy required by the device/circuit to operate is the main aim of this paper. Here the new design is implemented to reduce the power consumption of the device using the triggering pulses. The proposed triggering method uses a complementary MOS transistor (pMOS and nMOS) as a voltage divider and ground leakage suppressor (i.e.);these designs are named as Trig01 and Trig10 designs. In Trig01 design the pair of CMOS is placed in the voltage divider part;similarly in Trig10 design the pair of CMOS is placed at the ground leakage suppressor part. Standard CMOS gates like NOT, NAND, NOR, EX-OR etc. are designed with these technologies and these gates are designed with 180 nm technology file in the cadence tool suite;compared to the normal CMOS gates, the Bi-Trig gate contains 4 inputs and 2 outputs. The two extra inputs are used as Bi-Trig control signaling inputs. There are 2 control inputs and thus 22 = 4 combination of controlling is done (i.e.);both pMOS and nMOS are ON, both pMOS and nMOS are OFF, pMOS ON and nMOS OFF and pMOS ON and nMOS ON. Depending on the usage of the circuit, the mode of operation is switched to any one of the combination. If the output of the circuit is not used anywhere in the total block, that specified circuit can be switched into idle mode by means of switched OFF both the pMOS and nMOS transistor in the control unit. This reduces the leakage current and also the power wastage of the circuits in the total block. Bi-Trig controlled circuit reduces the power consumption and leakage power of the circuit without affecting a performance of the circuits.

Multisim 14.0在电子设计课程中的应用研究——以数字时钟电路为例

为提高电子设计课程的教学效果,帮助学生依照电路原理进行虚拟实验,以数字时钟设计教学为例,研究在电子设计课程中应用Multisim14.0进行电路设计、仿真、修改、元器件封装及PCB制作。实践结果表明,在电子设计课程中应用Multisim 14.0可以夯实学生的理论知识,提高学生的实践能力,提升电子设计课程的教学效果。

模拟乒乓球运动的逻辑电路设计

阐述在数字逻辑电路实验教学中引入游戏电路设计。以模拟乒乓球游戏电路的设计为例,该游戏电路综合运用计数器、移位寄存器、锁存器等逻辑器件,利用按键模拟两位选手的乒乓球拍,利用发光二极管模拟乒乓球及其运动路径,A端与B端相互击球,数码管显示选手的当前得分,游戏难度可通过改变时钟电路的频率进行调节。

铯原子钟电子倍增器可调高压电源设计

电子倍增器用来放大并输出铯原子的跃迁信号。倍增器电源是其重要组成部分,针对电子倍增器在增益变化及衰减情况下的供电需求,提出了一种基于分流调整电路结合倍压整流电路的高压电源设计方案,该方案在低压部分采用分流调整技术实现了电源输出电压控制;采用变压器结合多级倍压整流电路对电压放大输出,实现了电源可调电压范围在-306~-3 150 V和低输出纹波,电源的遥测电路实现了输出电压遥测。星载铯原子钟经过长期在轨测试,测试结果表明,本设计的电源在控制范围内实现了宽范围电压输出和遥测,低于3.23 V的电源纹波,保证了铯原子钟稳定度指标。

一种高速时钟分配电路单粒子效应测试系统设计

时钟分配电路是电子系统中信号处理单元参考时钟及多路时钟分配的关键元器件,其跟随系统在宇宙空间中容易受宇宙射线辐照发生单粒子效应,进而影响系统性能指标甚至基本功能。为此,提出一种针对数字单元翻转的微测试方法,结合分段存储技术完成高速时钟分配电路的单粒子效应的在线测试系统设计。另外,在HI-13串列加速器与HIRFL回旋加速器上进行了试验验证,成功监测到单粒子翻转、单粒子功能中断等典型单粒子效应。最后根据试验数据并结合FOM方法进行了电路在轨故障率推算,这对于集成电路研制阶段的测试评估与应用阶段的系统验证都有重要意义。

面向CMUT换能器的驱动电路设计与优化

电容式微机械超声换能器(CMUT)具有良好的电声特性、体积小、容易制作阵列等优势,在医学和船舶领域具有广泛的应用前景。论文针对自主研制的一种密排结构CMUT超声换能器的驱动需求,设计了基于FPGA和以MAX14808芯片为核心的驱动电路。用该电路产生方波脉冲,在单端时钟、差分时钟、透明模式下进行了相差角、延迟时间、CMUT收发测试,比较了优缺点。测试结果表明,驱动电路的输出与INP1/INN1输入之间的相差角一致、单端和差分时钟模式下输出与INP1/INN1输入之间的延迟时间差距较小。收发测试时,接收信号随着距离的增加呈指数型衰减,随着输入电压的增加基本呈线性增加且有较小弧度,单端时钟模式的稳定性最好。驱动电路的时钟模式设计,能够重新同步主控芯片的所有数据输入,以减少与FPGA输出信号相关的相位噪声。论文为水下和医疗的超声成像系统提供了硬件支持,为CMUT测试研究提供方法。

一种基于电容充放电的低功耗时钟发生器

基于SMIC 0.18μm CMOS工艺,设计了一种基于电容充放电的新型低功耗时钟发生器。为了减小温度变化引起的频率波动,设计了负温度系数偏置电路。采用了传统的占空比调节电路,可调节振荡波形的占空比。仿真结果显示,在3.3 V电源电压下,该振荡器可以稳定输出7.16 MHz频率的信号,相位噪声为-104.4 dBc/Hz,系统功耗为1.411 mW,其中环形振荡器功耗为0.811 mW。在-40℃~110℃温度变化范围内,振荡器的频率变化为7.116~7.191 MHz,容差在1.05%以内。同其他时钟发生器相比,该电路具有结构简单、功耗低,以及在宽温度范围内具有较高的频率稳定性等显著特点,能够满足芯片的工作要求,为芯片提供稳定时钟。

面向高性能计算机光互连的低抖动Retimer电路

随着通信带宽的大幅提升,低抖动作为多场景应用中信号传输质量的关键指标,已成为信号完整性研究的重要方向。56 Gbaud的Retimer芯片是高性能计算机光互连数据传输的关键核心芯片,其抖动性能也制约着光模块高性能计算机的整体性能。针对传统高速Retimer芯片抖动性能低的难题,首次提出了数据速率超过100 Gbps的低抖动Retimer电路。Retimer电路基于CDR+PLL架构,集成在光纤中继器中,具有均衡和全速率重定时功能;采用抖动消除的滤波电路,能在高噪声输入信号下取得良好的输出数据抖动性能,为解决传统Retimer直接采样转发导致输出数据抖动大的问题提供了技术支持。采用TSMC 28 nm CMOS工艺完成了基于CDR+PLL架构的低抖动Retimer电路设计。仿真结果表明,当输入112 Gbps PAM4时,Retimer的输出数据抖动为741 fs,相比于传统Retimer结构降低了31.4%。

电子式互感器辐射发射超标诊断及整改方法

电子式互感器是一种配电装置,由连接到传输系统和二次转换器的一个或多个电压或电流传感器组成,向仪器、继电保护或者控制装置传输正比于被测物理量的数值。一组电子式互感器共用一台合并通信单元。合并通信单元将来自变送段的电流或电压采样数据与采样时间进行相关的组合,并按约定的通信协议以数据帧的形式连续发送至以太网。依据GB/T 20840.8—2007标准规定的辐射发射试验来考核某型号电子式互感器时,发现其合并通信单元存在电磁辐射干扰超标现象。通过分析超标频点的干扰形成原因,采用了时钟扩频技术对产品电路进行改进,解决了问题,并得出了采用时钟扩频技术来抑制高频辐射骚扰的解决方案。