[ Objective] This paper aimed to study the effects of different facilities on laying performance, egg quality and air quality for commercial layers under free range system. [Metbod] The single factorial arrangement wa...[ Objective] This paper aimed to study the effects of different facilities on laying performance, egg quality and air quality for commercial layers under free range system. [Metbod] The single factorial arrangement was used in the tdal. 2 800 commercial Beijing You Chicken （BYC） at 23 weeks of age were chosen and randomly divided into four groups, three replicates each group, and 210 birds each replicate. The layers lived in loose housing condition with deep litter inside. Group 1 was the control, equipped with standard laying boxes, and flat-type perches; group 2 was e- quipped with common laying boxes, and flat-type perches; group 3 was equipped with common laying boxes, and erect-type perches, and group 4 was equipped with standard laying boxes, and erect-type perches. The laying performance, laying position and egg quality of birds during 24 to 32 weeks of age were recorded and measured, and average NH3, CO~ concentration of each group at 32 weeks of age were measured and detected. [Result] The results showed that laying performance of commercial BYC under loose housing condition were significantly different during 24 -32 weeks of age. The laying rate of the control group equipped with flat-type porches and standard laying boxes （33.25%） was significantly higher than in group equipped with flat-type perches and common laying boxes （21.83%） （P〈0.05）, and other two groups （26.04% and 27.48%） （P 〈0.05）. The ratio of floor eggs was significantly lower in groups with standard laying boxes than in the groups with common laying boxes （P 〈0. 05）, and the laying proportion in the first floor of layer boxes were much higher than those in the second floor （ P 〈 0.05）. There were no significant differences on egg quality among the groups （P〉0.05）. Average NH3, CO2 concentration of group 3 and 4 at 82 weeks of age were both signifi- cantly higher than of group 1 and 2 （P 〈0.05）. [ Conclusion] All of the above indicated that the utilization of facilities could improve layer＇s laying rate, especially with flat-type perches and standard laying boxes, and the indoor air quality was also affected to some extent.展开更多
We demonstrate a highly compact third-order elliptical micro-ring add-drop filter based on a silicon-on-insulator wafer. The elliptical micro-ring resonator has a major radius of 6μm （minor radius of 4.112μm） and ...We demonstrate a highly compact third-order elliptical micro-ring add-drop filter based on a silicon-on-insulator wafer. The elliptical micro-ring resonator has a major radius of 6μm （minor radius of 4.112μm） and a large free spectral range of 18 nm. Experimental results show a box-like channel dropping response, which has a 3 dB bandwidth of -2.7nm, high out-of-band signal rejection of around 40dB and a very low drop loss （〈0.5dB）. Simulation agrees well with the experiments. The footprint of the whole chip is only 0.0003mm2.展开更多
Distortion-free data embedding is a technique which can assure that not only the secret data is correctly extracted but also the cover media is recovered without any distortion after secret data is extracted completel...Distortion-free data embedding is a technique which can assure that not only the secret data is correctly extracted but also the cover media is recovered without any distortion after secret data is extracted completely. Because of these advantages, this technique attracts the attention of many researchers. In this paper, a new distortion-free data embedding scheme for high dynamic range （HDR） images is proposed. By depending on Cartesian product, this scheme can obtain higher embedding capacity while maintaining the exactly identical cover image and stego image when using the tone mapping algorithms. In experimental results, the proposed scheme is superior to Yu et aL＇s scheme in regard to the embedding rate——an average embedding rate of 0.1355 bpp compared with Yn et aL＇s scheme （0.1270 bpp）.展开更多
<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber re...<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div>展开更多
We describe modeling the solid-state dye laser with the microcavity size comparable to light wavelength. Certain symmetry in the allocation of gain material leads to depletion of odd longitudinal modes that, in turn, ...We describe modeling the solid-state dye laser with the microcavity size comparable to light wavelength. Certain symmetry in the allocation of gain material leads to depletion of odd longitudinal modes that, in turn, increases the tunability range of the microlaser. We provide simple physical explanation for the modeling results.展开更多
This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter（ADC）,which is optimized for high spurious free dynamic range（SFDR） performance and low power dissipation.With a 4.9 MHz ...This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter（ADC）,which is optimized for high spurious free dynamic range（SFDR） performance and low power dissipation.With a 4.9 MHz sine wave input,the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration.The ADC,with a total die area of 3.1×2.1 mm^2,demonstrates a maximum signal-to-noise distortion ratio（SNDR） and SFDR of 66.32 and 83.38 dB,respectively,at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.展开更多
A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plu...A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plus distortion（SNDR） with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC（residue amplification circuit）stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.展开更多
基金supported by the National Natural Science Funds(No.30972128)Beijing Natural Scince Funds(No.6102010)
文摘[ Objective] This paper aimed to study the effects of different facilities on laying performance, egg quality and air quality for commercial layers under free range system. [Metbod] The single factorial arrangement was used in the tdal. 2 800 commercial Beijing You Chicken （BYC） at 23 weeks of age were chosen and randomly divided into four groups, three replicates each group, and 210 birds each replicate. The layers lived in loose housing condition with deep litter inside. Group 1 was the control, equipped with standard laying boxes, and flat-type perches; group 2 was e- quipped with common laying boxes, and flat-type perches; group 3 was equipped with common laying boxes, and erect-type perches, and group 4 was equipped with standard laying boxes, and erect-type perches. The laying performance, laying position and egg quality of birds during 24 to 32 weeks of age were recorded and measured, and average NH3, CO~ concentration of each group at 32 weeks of age were measured and detected. [Result] The results showed that laying performance of commercial BYC under loose housing condition were significantly different during 24 -32 weeks of age. The laying rate of the control group equipped with flat-type porches and standard laying boxes （33.25%） was significantly higher than in group equipped with flat-type perches and common laying boxes （21.83%） （P〈0.05）, and other two groups （26.04% and 27.48%） （P 〈0.05）. The ratio of floor eggs was significantly lower in groups with standard laying boxes than in the groups with common laying boxes （P 〈0. 05）, and the laying proportion in the first floor of layer boxes were much higher than those in the second floor （ P 〈 0.05）. There were no significant differences on egg quality among the groups （P〉0.05）. Average NH3, CO2 concentration of group 3 and 4 at 82 weeks of age were both signifi- cantly higher than of group 1 and 2 （P 〈0.05）. [ Conclusion] All of the above indicated that the utilization of facilities could improve layer＇s laying rate, especially with flat-type perches and standard laying boxes, and the indoor air quality was also affected to some extent.
基金Supported by the National High Technology Research and Development Program of China under Grant No 2015AA016904the National Key Research and Development Plan of China under Grant No 2016YFB0402502the National Natural Science Foundation of China under Grant No 61275065
文摘We demonstrate a highly compact third-order elliptical micro-ring add-drop filter based on a silicon-on-insulator wafer. The elliptical micro-ring resonator has a major radius of 6μm （minor radius of 4.112μm） and a large free spectral range of 18 nm. Experimental results show a box-like channel dropping response, which has a 3 dB bandwidth of -2.7nm, high out-of-band signal rejection of around 40dB and a very low drop loss （〈0.5dB）. Simulation agrees well with the experiments. The footprint of the whole chip is only 0.0003mm2.
文摘Distortion-free data embedding is a technique which can assure that not only the secret data is correctly extracted but also the cover media is recovered without any distortion after secret data is extracted completely. Because of these advantages, this technique attracts the attention of many researchers. In this paper, a new distortion-free data embedding scheme for high dynamic range （HDR） images is proposed. By depending on Cartesian product, this scheme can obtain higher embedding capacity while maintaining the exactly identical cover image and stego image when using the tone mapping algorithms. In experimental results, the proposed scheme is superior to Yu et aL＇s scheme in regard to the embedding rate——an average embedding rate of 0.1355 bpp compared with Yn et aL＇s scheme （0.1270 bpp）.
文摘<div style="text-align:justify;"> We propose a novel scheme, based on digital-heterodyne optical phase-locked loop with whole-fiber circuit, to dynamically measure the free-spectral-range of a fiber resonator. The optical phase-locked loop is established with a differential frequency-modulation module consists of a pair of acousto-optic modulators. The resonance-tracking loop is derived with the Pound-Drever-Hall technique for locking the heterodyne frequency of the OPLL on the frequency difference between adjacent resonance modes. A stable locking accuracy of about 7 × 10<sup>?9</sup> and a dynamic locking accuracy of about 5 × 10<sup>?8</sup> are achieved with the FSR of 8.155 MHz, indicating a bias stability of the resonator fiber optic gyro of about 0.1?/h with 10 Hz bandwidth. In addition, the thermal drift coefficient of the FSR is measured as 0.1 Hz/?C. This shows remarkable potential for realizing advanced optical measurement systems, such as the resonant fiber optic gyro, and so on. </div>
文摘We describe modeling the solid-state dye laser with the microcavity size comparable to light wavelength. Certain symmetry in the allocation of gain material leads to depletion of odd longitudinal modes that, in turn, increases the tunability range of the microlaser. We provide simple physical explanation for the modeling results.
文摘This paper describes a 12-bit 40 MS/s calibration-free pipelined analog-to-digital converter（ADC）,which is optimized for high spurious free dynamic range（SFDR） performance and low power dissipation.With a 4.9 MHz sine wave input,the prototype ADC implemented in a 0.18-μm 1P6M CMOS process shows measured differential nonlinearity and integral nonlinearity within 0.78 and 1.32 least significant bits at the 12-bit level without any trimming or calibration.The ADC,with a total die area of 3.1×2.1 mm^2,demonstrates a maximum signal-to-noise distortion ratio（SNDR） and SFDR of 66.32 and 83.38 dB,respectively,at a 4.9 MHz analog input and a power consumption of 102 mW from a 1.8 V supply.
文摘A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plus distortion（SNDR） with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC（residue amplification circuit）stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.
