A high frequency vibration compensation approach for ultrahigh resolution SAR imaging based on sinusoidal frequency modulation Fourier-Bessel transform

Ultrahigh resolution synthetic aperture radar(SAR)imaging for ship targets is significant in SAR imaging,but it suffers from high frequency vibration of the platform,which will induce defocus into SAR imaging results.In this paper,a novel compensation method based on the sinusoidal frequency modulation Fourier-Bessel transform(SFMFBT)is proposed,it can estimate the vibration errors,and the phase shift ambiguity can be avoided via extracting the time frequency ridge consequently.By constructing the corresponding compensation function and combined with the inverse SAR(ISAR)technique,well-focused imaging results can be obtained.The simulation imaging results of ship targets demonstrate the validity of the proposed approach.

A Novel Clock Feedthrough Frequency Compensation for Fast-Settling of Folded-Cascode OTA

Based on the minimum settling time （MST） theory and step-response analysis of the second order system in active switched capacitor （SC） networks, a novel clock feedthrough frequency compensation （CFFC） method for a folded-cascode OTA is proposed. The damping factor r/is adjusted by using MOS capacitors to introduce clock feedthrough so that the OTA can obtain the MST state and thus achieve fast settling. Research results indicate that the settling time of the compensated OTA is reduced by 22.7% ;as the capacitor load varies from 0.5 to 2.5pF,the improved settling time increases approximately linearly from 3.62 to 4.46ns： for VGA application, fast settling can also be achieved by modifying the MOS capacitor value accordingly when the closed loop gain of the compensated OTA varies.

Frequency compensation control method for opposedpiston two-stroke folded-cranktrain engine's common rail system by loop-shaping theory

A frequency compensation control method for the opposed-piston two-stroke folded-cranktrain（ OPFC） diesel engine＇s common rail system is presented as a result of the study of the loop-shaping theory. A common rail working process and the classical frequency control theory are combined to construct a frequency restriction of common rail pressure. A frequency compensator is utilized to improve the robustness of multiplicative perturbations and disturbance. The loop-shaping method has been applied to design the common rail pressure controller of the OPFC diesel engine. Simulation and bench test results show that in the condition of perturbation that comes from the effect of injection,multi-injection,fuel pumping of a pre-cylinder,and instantaneous pressure fluctuation,the controller indicates high precision. Compared with the original controller,this method improves the control precision by 67. 3%.

Nested Miller Active-Capacitor Frequency Compensation for Low-Power Three-Stage Amplifiers

A new frequency compensation technique for low-power, area-efficient multistage amplifiers is introduced. Using nested active capacitors, our scheme achieves better bandwidth-to-power and slew-rate-to-power performances than previous works. Implemented in standard 0.35μm CMOS technology, our three-stage amplifier achieves 105dB DC gain, 3.3M GBW,68 phase margin, and 2.56V/μs average slew rate under a 150pF capacitive load. All of these are realized with only 40μW power consumption under a 2V power supply,with very small compensation capacitors.

A nonlinear model reference adaptive inverse control algorithm with pre-compensator

In this paper, the reduced-order modeling （ROM） technology and its corresponding linear theory are expanded from the linear dynamic system to the nonlinear one, and H∞ control theory is employed in the frequency domain to design some nonlinear system＇ s pre-compensator in some special way. The adaptive model inverse control （AMIC）theory coping with nonlinear system is improved as well. Such is the model reference adaptive inverse control with pre-compensator （PCMRAIC）. The aim of that algorithm is to construct a strategy of control as a whole. As a practical example of the application, the nunlerical simulation has been given on matlab software packages. The numerical result is given. The proposed strategy realizes the linearization control of nonlinear dynamic system. And it carries out a good performance to deal with the nonlinear system.

Analysis and compensation of low frequency characteristics of sensors for vibration testing

In view of the influence and harm of low frequency vibration environment on the structure of spaceflight products,a low frequency dynamic study method for piezoelectric sensor based on the dynamic system of sinusoidal pressure is proposed.This method uses a sinusoidal pressure dynamic system with two-way dual channel import and export synchronization technology to study the low frequency characteristics of a piezoelectric sensor of PCB company,and its lower cut-off frequency is 0.26 Hz.It is also studied that when the frequency of the measured vibration or shock signal is 1-200 kHz,the error range of signal positive pressure action time is 4.87%-0.03%.The dynamic compensation for the low frequency of the vibration sensor is carried out,and the compensation effect is good.

Low-Power Three-Stage Amplifier Using Active-Feedback Miller Capacitor and Serial RC Frequency Compensation

A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which significantly deteriorates the stability of the amplifier. The serial RC stage introduced as the second stage output load can optimize the resistor Rz and the capacitor Cz under fixed power and small compensation capacitor Ca, which brings about a suitable Q-value of the complex-pole and the gain-bandwidth product extension of the amplifier. The amplifiers were designed and implemented in a standard 65 nm CMOS process with capacitive loads of 500 p F and 2 n F, respectively. The post-layout simulation results show that the amplifier driving the 500 p F capacitive load can achieve a gain of 113 d B, a phase margin of 50.6° and a gain-bandwidth product of 5.22 MHz while consuming 24 μW from a 1.2 V supply. For the 2 n F capacitive load, the amplifier has a gain of 102 d B, a phase margin of 52.8°, a gain-bandwidth product of 4.41 MHz and a power of 43 μW. The total compensation capacitors are equal to 1.13 p F and 1.03 p F. The better figures-of-merits are 108 750 and 205 113(MHz×p F/m W). The layout areas are 0.064 mm×0.026 mm and 0.063 mm×0.027 mm. Compared with the CFCC scheme, the gainbandwidth product is extended by 1.6 times at CL=500 p F and Ca=1.1 p F.

A Current-Mode DC-DC Buck Converter with High Stability and Fast Dynamic Response

A current-mode DC-DC buck converter with high stability is presented. The loop gain＇s expression of the current-mode converter is derived by employing an advanced model of a current-mode control converter. After analyzing the loop gain＇s expression, which illustrates the method of selecting suitable frequency compensation for the control loop,a novel pole-zero tracking frequency compensation is proposed. Based on theoretical analysis, a DC-DC buck converter with high stability is designed with 0.5μm-CMOS technology. The simulated results reveal that the stability of the converter is independent of the load current and the input voltage. Moreover,the converter provides a full load transient response setting time of less than 5μs and overshoots and undershoots of less than 30mV.

Analysis and Design of a High-Stability,High-Accuracy,Low-Dropout Voltage Regulator

A high-accuracy,low-dropout （LDO） voltage regulator is presented. Using the slow-rolloff frequency compensation scheme, the LDO effectively overcomes the stability problem, facilitates the use of a ceramic capacitor, and improves the output voltage accuracy, which is critical for powering high-performance analog circuitry. The slow-rolloff compensation scheme is realized by introducing three pole-zero pairs, including the proposed polezero pair and sense zero. The post-layout simulation results demonstrate that this LDO has robust system stability, a high open-loop gain, and a high unit-gain frequency,which lead to excellent regulation and transient response performance. The line and load regulation are 27μV/V and 3.78μV/mA, and the overshoots of the output voltage are less than 30mV,while the dropout voltage is 120mV for a 150mA load current.

A Three-Stage Operational Amplifier for a Wide Range of Capacitive Loads

This paper presents a three-stage CMOS operational amplifier （opamp） that combines accuracy with stability for a wide range of capacitive loads. A so-called quenching capacitor is added to a multipath nested Miller compensation （MNMC） topology to obtain stability for a wide range of capacitive loads. Theoretical analysis and mathematical formulas are provided to prove the improvement in stability. A prototype of this frequency compen- sation scheme is implemented in a 0.7μm CMOS process. Measurement′s show that the amplifier can drive capaci- tive loads ranging from 100pF to 100/μF with a gain of 90dB and a minimum phase margin of 26°. The amplifier has a unity-gain bandwidth of 1MHz for a 100pF capacitive load. It employs a quenching capacitance of 18pF.

A clock synchronization method based on IEEE 1588 and its implementation on Ethernet

We presented a clock synchronization method that contained a clock adjusting algorithm and a frequency compensated clock to achieve precise synchronization among distributed clocks based on IEEE 1588 protocol.Further,we presented its application on Ethernet and implementation of the frequency compensated clock in a field programmable gate array(FPGA) as experiments.The results indicate that this method can support sub-microsecond synchronization with inexpensive standard crystal oscillators.

A mobility compensation method for drones in SG-eloT

In order to achieve the specific goal of a smart grid,the concept of electricity Internet of Things(eloT)has been proposed to assist the monitoring and inspection of power transmission line state and optimize the asset utilization.The long power transmission line and the complex field operation environment urge the introduction of drones into the eloT for fast power transmission line inspection,data collection from sensors for further big data analysis,adaptive control of power line voltage,etc.Additionally,drones can also act as a central communication control or relay point to serve the data exchange among sensors,drones and power transmission line maintenance personnel in the scenario where the conventional mobile communication service is not available.However,the fast mobility of drones may affect the signal transmission and position estimation performance,which may further deteriorate the networking performance.In order to solve this problem,a mobility compensation method is proposed,which includes the steps of frequency offset estimation and relative velocity calculation.Through the Monte Carlo simulations,the proposed algorithm shows favorable gains compared with the conventional ones.

New design of high-precision oven controlled crystal oscillator

Combining oven controlled technique,digital compensation,high-resolution frequency difference measurement and self-calibration technique,a new design method of precise oven controlled crystal oscillator（OCXO） is proposed.Fine compensation is made in the vicinity of the crystal temperature inflection point by using the non-real-time temperature compensation strategy,and self-calibration system is integrated in the crystal.The method improves the digital compensated phase noise,simplifies the traditional OCXO development system,reduces the cost and shortens the developing cycle.Experiment results show that with a standard reference signal and self-calibration updated data,the oscillator can work stable and achieve its best performence.The performance index of crystal oscillator had an improvement with one to two orders of magnitude on the basis of original technical index.The method is widely used in the improvement of high-end crystal oscillator and atomic clock.

Decoder-based transient signal post-processing for ITU-T G.719 at low bit rate

Associated with ITU-T G.719,a post-processing method in frequency domain for enhancing the perceptual quality of the decoded transient audio is proposed only to the audio decoder with no side information from the encoder.The proposed post-filter is used to filter the frequency coefficients of the decoded transient frame and consists of a short-term post-filter and a spectral tilt compensation filter which are derived from linear predictive coding（LPC） predictor based on the discrete cosine transform（DCT） coefficients of the decoded transient frame.As a result,the post-filter in frequency domain shapes the temporal noise in time domain and controls the pre-echo noise effectively while enhancing the transient perception.Listening test results show that the preferring ratio of the post-processed transient signal is higher than that of the original decoded signal at a low bit rate of 32 kbit/s in G.719 and the post-processing module brings a complexity of 12.399 WMOPS to the decoder.

Full on-chip and area-efficient CMOS LDO with zero to maximum load stability using adaptive frequency compensation

A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising the LDO＇s stability in the full output current range. Meanwhile, the use of a compact pass transistor （the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique） has enabled the LDO to be very areaefficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 × 320/zm^2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.

A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.

On-chip frequency compensation with a dual signal path operational transconductance amplifier for a voltage mode control DC/DC converter

A novel onchip frequency compensation circuit for a voltagemode control DC/DC converter is pre sented. By employing an RC network in the two signal paths of an operational transconductance amplifier （OTA）, the proposed circuit generates two zeros to realize high closedloop stability. Meanwhile, full onchip integration is also achieved due to its simple structure. Hence, the number of offchip components and the board space is greatly reduced. The structure of the dual signal path OTA is also optimized to help get a better transition response. Im plemented in a 0.5 #m CMOS process, the voltage mode control DC/DC converter with the proposed frequency compensation circuit exhibits good stability. The test results show that both load and line regulations are less than 0.3%, and the output voltage can be recovered within 15 #s for a 400 mA load step. Moreover, the compensation components area is less than 2% of the die＇s area and the board space is also reduced by 11%. The efficiency of the whole chip can be up to 95%.

Passive phase noise compensation for fiber-optic radio frequency transfer with a nonsynchronized source

We propose a passive compensation fiber-optic radio frequency（RF） transfer scheme with a nonsynchronized RF stable source during a round-trip time, which can avoid high-precision phase-locking and efficiently suppress the effect of backscattering only using two wavelengths at the same time. A stable frequency signal is directly reproduced by frequency mixing at the remote site. The proposed scheme is validated by the experiment over a 40 km single mode fiber spool using nonsynchronized common commercial RF sources. The influence of the stability of nonsynchronized RF sources on the frequency transfer is investigated over different length fiber links.

A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC（automatic gain control） and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL（sound pressure level）.Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power（48μW at 1.4 V） can be easily achieved in a high threshold-voltage CMOS process of 0.35μm（V（TON） ＋ ｜V（TOP）｜≈1.35 V）.The THD is below -45 dB.The fabricated chip only occupies the area of 1×0.5 mm^2 and 1×1 mm^2.

A very low noise preamplifier for extremely low frequency magnetic antenna

Besides the electrode-pair antenna,the magnetic antenna is also used for the extremely low frequency （ELF） submarine communication.To receive the weak ELF signals,the structure of a small sized magnetic antenna determines its specific electrical characteristics.The ELF magnetic antenna shows high internal resistance, alternating-current impedance,and a resonance frequency near the operating bandwidth.In accordance with the electrical characteristics of ELF magnetic antenna,a low noise preamplifier and frequency compensation circuit were designed and realized.The preamplifier is a three-stage negative feedback circuit,which is composed of parallel JFET,common-emitter amplifier with a Darlington structure and a common-collector amplifier in push-pull connection.And a frequency compensation circuit is cascaded to compensate the characteristic in low frequency range.In the operating bandwidth f = 30-200 Hz,the circuit has a gain of 39.4 dB.The equivalent input noise is 1.97 nV/Hz^（1/2） and the frequency response keeps flat in operating bandwidth.The proposed preamplifier of the ELF magnetic antenna performs well in receiving ELF signals.