Residual Phase Noise and Time Jitters of Single-Chip Digital Frequency Dividers

In this paper, we demonstrate the residual phase noise of a few microwave frequency dividers which usually limit the performance of frequency synthesizers. In order to compare these dividers under different operation frequencies, we calculate additional time jitters of these dividers by using the measured phase noise. The time jitters are various from -0.1 fs to 43 fs in a bandwidth from 1 Hz to 100 Hz in dependent of models and operation frequencies. The HMC series frequency dividers exhibit outstanding performance for high operation frequencies, and the time jitters can be sub-fs. The time jitters of SP8401, MC10EP139, and MC100LVEL34 are comparable or even below that of HMC series for low operation frequencies.

A 83 GHz InP DHBT static frequency divider

A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18μm CMOS process

With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of the hot spots in current research. This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications. High-speed divider-by-2 with traditional source- coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. A-E modulator is achieved by an improved MASH 1-1-1 structure. This structure has excellent performance in many ways, such as noise, spur and input dynamic range. Fabricated in TSMC 0.18/tin CMOS process, the fractional-N frequency divider occupies a chip area of 1130 × 510μm^2 and it can correctly divide within the frequency range of 0.8-9 GHz. With 1.8 V supply voltage, its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.

A broadband regenerative frequency divider in InGaP/GaAs HBT technology

A dynamic divide-by-two regenerative GaP/GaAs heterojunction bipolar transistors （HBTs） frequency divider （RFD） is presented in a 60-GHz-fT Intechnology. To achieve high operation bandwidth, active loads instead of resistor loads are incorporated into the RFD. On-wafer measurement shows that the divider is operating from 10 GHz up to at least 40 GHz, limited by the available input frequency. The maximum operation frequency of the divider is found to be much higher than fT/2 of the transistor, and also the divider has excellent input sensitivity. The divider consumes 300.85 mW from 5 V supply and occupies an area of 0.47 × 0.22 mm^2.

An InGaAs/InP 40 GHz CML static frequency divider

Static frequency dividers are widely used as a circuit performance benchmark or figure-of-merit indicator to gauge a particular device technology’s ability to implement high speed digital and integrated high performance mixed-signal circuits.We report a 2：1 static frequency divider in InGaAs/InP heterojunction bipolar transistor technology.This is the first InP based digital integrated circuit ever reported on the mainland of China. The divider is implemented in differential current mode logic（CML） with 30 transistors.The circuit operated at a peak clock frequency of 40 GHz and dissipated 650 mW from a single -5 V supply.

A 220 GHz dynamic frequency divider in 0.5μm InP DHBT technology

A high performance 3 inch 0.5 μm InP DHBT technology with three interconnecting layers has been developed.The epitaxial layer structure and geometry parameters of the device were carefully studied to get the required performances.The 0.5 × 5 μm^2 InP DHBTs demonstrated ft = 350 GHz,f（max） = 532 GHz and BV（CEO） = 4.8 V,which were modeled using Agilent-IIBT large signal model.As a benchmark circuit,a dynamic frequency divider operating from 110 to 220 GHz has been designed,fabricated and measured with this technology.The ultra-high-speed 0.5 μm InP DHBT technology offers a combination of ultra-high-speed and high breakdown voltage,which makes it an ideal candidate for next generation 100 GHz＋ mixed signal integrated circuits.

A Ka-band wide locking range frequency divider with high injection sensitivity

This paper proposes a direct injection-locked frequency divider（ILFD） with a wide locking range in the Ka-band. A complementary cross-coupled architecture is used to enhance the overdriving voltage of the switch transistor so that the divider locking range is extended efficiently. New insights into the locking range and output power are proposed. A new method to analyze and optimize the injection sensitivity is presented and a layout technique to reduce the parasitics of the cross-coupled transistors is applied to decrease the frequency shift and the locking range degradation. The circuit is designed in a standard 90-nm CMOS process. The total locking range of the ILFD is 43.8% at 34.5 GHz with an incident power of –3.5 dBm. The divider IC consumes 3.6 mW of power at the supply voltage of 1.2 V. The chip area including the pads is 0.50.5 mm2.

A 7-27 GHz DSCL divide-by-2 frequency divider

This paper presents the design and analysis of a high speed broadband divide-by-2 frequency divider. The proposed divider is a dynamic source-coupled logic（DSCL） structure formed with two dynamic-loading master-slave D latches,which enables high frequency operation and low power consumption.This divider exhibits a wide locking range from 7-27 GHz and the minimum power consumption is only 1.22 mW from a 1.2 V supply.The input sensitivity is as low as -25.4 dBm across the operating frequency range.This chip occupies 685×430μm^2 area with two on-chip spiral inductors in 90 nm CMOS process.

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler（DMP） and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm^2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.

A 37 GHz wide-band programmable divide-by-N frequency divider for millimeter-wave silicon-based phase-locked loop frequency synthesizers

A 37 GHz wide-band programmable divide-by-N frequency divider(FD) composed of a divide-by-2 divider(acting as the first stage) and a divider with a division ratio range of 273–330(acting as the second stage) has been designed and fabricated using standard 90 nm CMOS technology. The second stage divider consists of a high-speed divide-by-8/9 dual-modulus prescaler, a pulse counter, and a swallow counter. Both the first stage divider(with high speed) and the divide-by-8/9 prescaler employ dynamic current-mode logic(DCML) structure to improve the operating performance. The first stage divider can work from 2 to 40 GHz and the whole divider covers a wide frequency range from 25 to 37 GHz. The input sensitivity is as low as-20 d Bm at 32 GHz and the phase noise at 37 GHz is less than-130 d Bc/Hz at an offset of 1 MHz. The whole chip dissipates 17.88 m W at a supply voltage of 1.2 V and occupies an area of only 730 μm×475 μm.

A novel wideband low phase noise 2:1 frequency divider

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider. Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques, the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm~2 of the core die area.

A 75 GHz regenerative dynamic frequency divider with active transformer using InGaAs/InP HBT technology

This letter presents a high speed 2 ： 1 regenerative dynamic frequency divider with an active transformer fabricated in 0.7μm InP DHBT technology with fTof 165 GHz and fmax of 230 GHz. The circuit includes a two-stage active transtbrmer, input buffer, divider core and output buffer. The core part of the frequency divider is composed of a double-balanced active mixer （widely known as the Gilbert cell） and a regenerative feedback loop. The active transformer with two stages can contribute to positive gain and greatly improve phase difference. Instead of the passive transformer, the active one occupies a much smaller chip area. The area of the chip is only 469 × 414μm2 and it entirely consumes a total DC power of only 94.6 mW from a single -4.8 V DC supply. The measured results present that the divider achieves an operating frequency bandwidth from 75 to 80 GHz, and performs a -23 dBm maximunl output power at 37.5 GHz with a 0 dBm input signal of 75 GHz.

A 31–45.5 GHz injection-locked frequency divider in 90-nm CMOS technology

We present a 31–45.5 GHz injection-locked frequency divider(ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 d Bm. The power consumption is 2.88 m W under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm×0.42 mm.

Pulse swallowing frequency divider with low power and compact structure

A pulse swallowing frequency divider with low power and compact structure is presented.One of the DFFs in the divided by 2/3 prescaier is controlled by the modulus control signal,and automatically powered off when it has no contribution to the operation of the prescaier.The DFFs in the program counter and the swallow counter are shared to compose a compact structure,which reduces the power consumption further.The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28×22μm;.The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.

A low power, low noise figure quadrature demodulator for a 60GHz receiver in 65-nm CMOS technology

This paper presents the design of a low power （LP） and a low noise figure （NF） quadrature demodula- tor with an on-chip frequency divider for quadrature local oscillator （LO） signal generation. The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology. On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance. The chip is implemented in 65-nm LP CMOS technology. The demod- ulator is designed for an input radio frequency （RF） band ranging from 10.25 to 13.75 GHz. A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency （IF） band ranging from DC to 1.75 GHz. From 10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain （VCG） ranging from 14.2 to 13.2 dB, and a minimum single-sideband N F （SSB-NF） of 9 dB. The measured third-order input intercept point （lIP3） is -3.3 dBm lbr a two-tone test frequency spacing of 1 MHz. The mixer alone draws a current of only 2.5 mA, whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply. The measurement results for a frequency divider, which was fabricated individually, prior to being integrated with the quadrature demodulator, in 65-rim LP CMOS technology, are also presented in this paper.

Low-Power CMOS VCO with Dual-Band Local Oscillating Signal Outputs for 5/2.5-GHz WLAN Transceivers

The paper describes a low-power CMOS voltage-controlled oscillator (VCO) with dual-band local oscillating (LO) signal outputs for 5/2.5-GHz wireless local area network (WLAN) transceivers. The VCO is based on an on-chip symmetrical spiral inductor and a differential varactor. The 2.5-GHz quadrature LO signals are generated using the injection-locked frequency divider (ILFD) technique. The ILFD structure is similar to the VCO structure with its wide tracking range. The design tool ASITIC was used to optimize all on-chip symmetrical inductors. The power consumption was kept low with differential LC tanks and the ILFD technique. The circuit was implemented in a 0.18-μm CMOS process. Hspice and SpectreRF simulations show the proposed circuit could generate low phase noise 5/2.5-GHz dual band LO signals with a wide tuning range. The 2.5-GHz LO signals are quadrature with almost no phase and amplitude errors. The circuit consumes less than 5.3 mW in the tuning range with a power supply voltage of 1.5 V. The die area is only 1.0 mm×1.0 mm.