A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop

In deep space exploration,many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible.In our paper,we analyze the possible frequency measurement points of the third-order phase-locked loop(PLL)and find a new Doppler measurement strategy.Based on this finding,a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained.In the actual data processing,compared with the existing engineering software,the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm.The improved algorithm is simple and easy to implement.This improvement can be easily combined with other improvement methods of PLL,so that the performance of PLL can be further improved.

基于改进型SOGI-FLL的单相并网逆变器电压控制方法

针对常规基于二阶广义积分发生器的锁频环(second-order generalized integrator based frequency locked-loop,SOGI-FLL)在单相并网逆变器电压控制中对直流及谐波分量抑制能力不足,从而引起输出电压频率、相位振荡的问题,提出一种基于改进型SOGI-FLL的单相并网逆变器电压控制方法。该方法在常规SOGI-FLL控制的基础上,在电压信号输入端加入级联型谐振滤波环节来消除谐波分量;同时引入直流控制环节,借助输入电压误差估计值来消除直流分量,达到电网电压频率和相位快速跟踪效果,从而实现电压的自适应控制。使用MATLAB及RT-LAB硬件在环半实物平台,在频率突变、含直流分量及谐波分量的非理想电网环境中,对二阶广义积分器锁相环、双二阶广义积分器锁频环与改进型SOGI-FLL 3种控制方法进行仿真及实验。结果表明,所提改进型SOGI-FLL控制方法在消除直流及谐波干扰的同时,能在0.025 s内实现频率锁定,且频率偏差小于2%,可增强系统对非理想电网信号的适应能力,实现并网电压的快速跟踪,具有良好动态性能。

基于ROGI-FLL的汽车充电站指定次谐波与无功优化

在能源转型背景下,电动汽车的应用呈爆发式增长,电动车集中式充电站的需求量也随之增长。由于汽车直流充电桩的整流装置,其开关模式使系统产生谐波,同时无功功率增加,功率因数降低。针对某电动汽车充电站,传统并联电容器补偿无法解决谐波干扰,提出通过降阶广义积分原理提取指定次谐波,结合静止同步补偿器在同步坐标系下双闭环补偿控制,加入锁频环节自适应跟踪电网频率,综合补偿谐波与无功功率。通过建模分析,结果补偿系统THD指数由28.65%降至3.64%,功率因数提高至0.95以上。

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications

A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.

Joint frequency offset tracking and PAPR reduction algorithm in OFDM systems

This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset（RCFO） using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop（MPLL） is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.

2.7-4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.

Pump-induced carrier envelope offset frequency dynamics and stabilization of an Yb-doped fiber frequency comb

In this paper, we demonstrate a carrier envelope phase-stabilized Yb-doped fiber frequency comb seeding by a nonlinear-polarization-evolution（NPE） mode-locked laser at a repetition rate of 60 MHz with a pulse duration of 191 fs.The pump-induced carrier envelope offset frequency（ f0） nonlinear tuning is discussed and further explained by the spectrum shift of the laser pulse. Through the environmental noise suppression, the drift of the free-running f0 is reduced down to less than 3 MHz within an hour. By feedback control on the pump power with a self-made phase-lock loop（PLL）electronics the carrier envelope offset frequency is well phase-locked with a frequency jitter of 85 m Hz within an hour.

TDTL Based Frequency Synthesizers with Auto Sensing Technique

This paper presents a frequency synthesizer architecture based on the time delay digital tanlock loop (TDTL). The loop is of the first order type. The synthesizer architecture includes an adaptation mechanism to keep the complete system in lock. The mechanism uses a frequency sensing structure to control critical TDTL parameters responsible for locking. Both integer and fractional multiples of the loop reference frequency are synthesized by the new architecture. The ability of the TDTL based frequency synthesizer to respond to sudden variations in the system input frequency is studied. The results obtained indicate the proposed synthesizer has a robust performance and is capable of responding to those changes provided that they are within the bounds of its locking region.

COMPARISON OF SIGMA-DELTA MODULATOR FOR FRACTIONAL-N PLL FREQUENCY SYNTHESIZER

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.

基于改进SOGI-FLL的旋转弹舵机滞后测试方法

针对旋转弹舵机滞后测试中存在的噪声及常值偏移问题,将2阶广义积分锁频环(SOGI-FLL)改进后应用于测试数据处理,以精确地得到舵机滞后角。舵机滞后角测试问题的本质是存在噪声及常值偏移下的正弦信号相位提取问题。通过在常规SOGI-FLL中引入常值偏移补偿回路,使其具有常值偏移扰动抑制能力。改进SOGI-FLL表现为带通滤波器特性,可实现正弦信号基波频率处无滞后无衰减的滤波,有效消除噪声及常值偏移的影响,其输出的正交信号供给带有PI环节的锁相环(PLL)进行相角估计。仿真和实验结果表明,在测试信号存在噪声及常值偏移时,相比于传统FFT方法和相关分析法,改进SOGI-FLL能够有效地提高滞后角处理精度。

基于SOGI-FLL的伺服传动系统谐振频率检测方法

在工业伺服控制领域,常采用陷波滤波器抑制机械谐振,而准确地获取谐振频率是谐振成功抑制的首要条件。采用二阶广义积分器-锁频环(SOGI-FLL)分析速度控制器输出信号以检测谐振频率。首先介绍了SOGI-FLL的基本结构及锁频环的工作原理,然后分析了幅值频率自适应SOGI-FLL的频率响应性能,最后通过仿真和试验验证了幅值频率自适应SOGI-FLL能准确且快速地测出谐振频率,将所测频率用于陷波滤波器参数设置,成功抑制了机械谐振。

基于SOGI-FLL/PLL光伏并网逆变器低电压穿越控制技术研究

采用了一种根据并网点电压跌落深度使逆变器发出一定无功功率,将基于二阶广义积分器(SOGI)的锁频环(FLL)和锁相环(PLL)相结合锁定相位,最终实现低电压穿越的方法,该方法利用SOGI-FLL提取频率信息实现锁频功能,为坐标变换提供相角信息,SOGI的陷波器特性滤除二次谐波,控制正负序电流内环的电流大小,进而控制输出有功和无功的大小,实现低电压穿越。仿真结果表明,该控制策略可以很好地滤除二次谐波,快速、精确地锁定相位,且具备低电压穿越能力。

应用于高性能延迟锁相环的占空比修正电路设计

设计了一款应用于高性能延迟锁相环的占空比修正电路。该电路主要由差分放大电路、占空比调整电路、缓冲器电路和占空比检测电路组成,采用TSMC 40 nm CMOS工艺和1.1 V的电源电压。仿真的结果表明,时钟频率2 GHz~8 GHz,占空比20%~80%的输入时钟信号,经过占空比修正电路调节后,输出时钟信号占空比变为50%±0.2%,可应用于高性能延迟锁相环中。

基于自适应增强型复系数滤波器的多电飞机变频电网状态估计

多电飞机的电网是一种典型的孤岛微网,具有360~800 Hz的宽频率工作范围,传统恒定频率电网同步方法的动态性能在飞机变频电网中有所不足。为了准确估计飞机变频电网的电网状态,结合自适应模块,对增强型复系数滤波器锁相环进行改进,设计了一种适应于MEA变频电网的自适应增强型复系数滤波器锁相环结构(AECCF-PLL)。分析了其传递函数与阶跃响应之间的关系,推导了模型参数与频率的关系,建立了频率自适应模块,满足飞机变频交流电网状态估计对稳定性和快速性的要求。实验结果表明,在飞机变频电网含有大小频率跳变、谐波、斜坡等扰动情况时,提出的AECCF-PLL可以实现对电网状态的快速稳定估计。

电网故障下含直驱风电机组的电力系统频率动态响应分析

电网受扰后基于模型解析的频率响应分析对电力系统安全评估与紧急控制具有重要意义。电网发生故障时,直驱风电机组(DDWT)并网点电压幅值跌落引发控制器暂态响应,同时电压相位突变引发锁相暂态响应,锁相暂态响应又通过变流器控制传导产生功率控制误差,可能导致现有以负荷突变场景为对象的频率特性分析产生较大偏差。为此,提出了电网故障下DDWT锁相偏差的量化方法;解析了锁相偏差经DDWT变流器控制的传导路径,提出了锁相暂态响应导致DDWT功率控制误差的机理及其计算方法;建立了电网故障下含DDWT的电力系统频率响应模型,提出了锁相暂态响应影响下系统频率变化率和最大频率偏差的计算方法,解析了电网故障下考虑DDWT功率控制误差的电力系统频率动态响应特性,并通过算例分析验证了所提方法的有效性。

基于SSO多扰动输入机理分析的DFIG-GSC功率振荡抑制策略研究

电网次同步振荡(SSO)已成为桎梏新能源发展的主要问题之一,针对SSO下双馈感应发电机(DFIG)中网侧变流器(GSC)的功率振荡问题展开研究。首先,建立SSO对GSC的多扰动输入数学模型,探究不同扰动输入的性质以及其对GSC系统的影响,明确了针对物理量扰动以及信号扰动分别采用补偿与滤除两种不同的抑制方法。其次,针对锁相环(PLL)输出误差经过坐标变换产生耦合振荡的问题,建立PLL输出误差角度的频域数学模型,并通过设计一种改进PLL消除其输出误差对GSC的信号扰动影响。同时,设计一种准谐振控制器的自适应算法,并提出基于自适应准谐振控制器的DFIG-GSC功率振荡抑制策略,消除SSO对GSC的物理扰动影响;最后,通过搭建具有SSO模拟环境的DFIG实验平台,验证本文所提控制策略的有效性。

带残余频偏的软扩频信号伪码序列盲估计

针对带残余频偏的软扩频信号伪码序列盲估计难的问题,提出一种奇异值分解(singular value decomposition,SVD)结合全数字锁相环(digital phase locked loop,DPLL)的方法。所提方法首先对待处理信号通过不重叠分段生成数据矩阵,每段信号长度为一倍伪码周期;然后利用其自相关矩阵的右上角元素估计失步点进行同步,并且在重新计算自相关矩阵后根据较大特征值个数估计进制数;最后通过多次快速SVD算法结合DPLL最终实现伪码序列的盲估计。仿真结果显示,所提方法在低信噪比条件下可以有效估计出带残余频偏的软扩频信号的伪码序列,并且性能优于其他对比方法。

一种适用于亚采样锁相环的高鲁棒性辅助锁定电路

当前的研究表明,基于亚采样相位检测器(Sub-Sampling Phase Detectors,SSPD)的锁相环(Phase-Locked Loop,PLL)相较传统锁相环架构可以实现显著降低的带内相位噪声。然而,在片上系统(Systems on Chip,SOCs)应用中,PLL容易受到衬底或电源耦合的干扰,这很可能会导致PLL失去锁定,且可能无法恢复。针对此问题,提出一种将辅助锁频环(Frequency-Locked Loop,FLL)和数字锁定检测器(Digital Lock Detector,DLD)相结合的适用于亚采样锁相环(Sub-Sampling Phase-Locked Loop,SSPLL)的高鲁棒性辅助锁定电路。仿真结果表明:与传统SSPLL相比,所提出的电路极大提升了PLL对衬底或电源干扰的鲁棒性,同时保持了其低相位噪声的优点,这对于SSPLL在大规模生产和应用中的可靠性具有重要意义。